Specifications
Altera Corporation 29
EPXA1 Development Board Hardware Reference Manual
f
For further details about booting the device from flash memory, refer to
the Excalibur Devices Hardware Reference Manual.
Using the Quartus II Software
The Quartus II software can generate an SRAM object file (.sof) containing
both hardware and software.
The Quartus II programmer uses the .sof file to configure the EPXA1
device via JTAG, using either the MasterBlaster or ByteBlasterMV
download cables.
f
For further details of how to create a .sof file and configure the EPXA1
device via JTAG, consult the Quartus II Help.
JTAG Interfaces
There are two JTAG connectors on the EPXA1 development board, as
shown in Figure 10
Figure 10. JTAG Interfaces on the EPXA1 Development Board
The JTAG connector, J6, is used to connect an Altera ByteBlaster or
MasterBlaster download cable. The Multi-ICE connector, J8, is used to
connect a Multi-ICE cable or any other compatible cable.
JTAG
connectors
(pin 1s
indicated)