Specifications

Altera Corporation 21
EPXA1 Development Board Hardware Reference Manual
 The expansion headers are on a common 0.1-inch pitch/spacing
to make it easier to use both headers together if desired.
Standard Expansion Header
The standard expansion header interface includes the following features:
■ 40 APEX
®
device general-purpose I/O signals
■ A buffered, zero-skew copy of the on-board OSC output
■ A buffered, zero-skew copy of the EPXA1’s PLL-output
■ An APEX device clock-input (for daughter cards that drive a clock to
the FPGA
■ An active-low power-on-reset signal
■ Three regulated 3.3-V power-supply pins
■ One regulated 5-V power-supply pin
■ Unregulated power-supply pin (connects directly to J1 power-input
plug)
■ Numerous ground connections
■ Card-select I/O
■ RC-filtered I/O
Long Expansion Header
The long expansion header interface shares the same characteristics as the
standard interface, and has the following additional pins in use:
■ Two regulated 3.3-V power-supply pins
■ Sixteen address pins
■ Sixteen data pins
Expansion Header Pin Details
In addition, the following points apply to either standard or long
expansion headers:
■ J9.38 and J15.38 can be used as a global card-enable signal
■ A low-current, 5-V power supply is presented on J4.2 and J11.2
■ The V
REF
voltage for the analog switches is presented on J10.3 and
J3.3.
■ The maximum current load on each header is 500 mA at 3.3 V, 50 mA
at 5 V and 100 mA at 12 V
■ The remaining pins on the expansion headers connect to user I/O
pins on the EPXA1 device. Table 24 on page 34 lists the expansion
header signal pin assignments