Specifications

14 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Serial I/O Interfaces
There can be two UARTs in the EPXA1 device. A dedicated UART is
located in the embedded stripe; optionally, an additional IP UART can be
implemented in the FPGA. If the IP UART is used, it is connected to 3.3-V
standard EPXA1 I/O pins. Each UART is connected to a transceiver (U6
for the embedded stripe UART and U1 for the IP UART) to translate
LVTTL voltage for RS-232 compatibility at up to 250 Kbps. Each UART
also has its own DB9 male RS-232 connector wired as a DTE.
 The transceiver uses a 3.3-V power supply. If the RS-232 input
pins are used as outputs, contention occurs because the bus
transceiver is always active. If these pins are not used as part of
a design, ensure that they remain in the high-impedance state.
All unused I/O pins can be set to tri-state mode in the Quartus II
software (see “Unused I/O Pins” on page 50).
See Table 23 on page 33 for information on the RS-232 signals.
Table 4 shows the UART interface characteristics.
Table 5 lists the UART LEDs on the EPXA1 development board.
Table 4. UART Interface Characteristics
Features I/O Pins Voltage (V)
UART 1 TX, RX & Control 8 3.3
UART 2 TX, RX & Control 8 3.3
Table 5. UART LEDs
Board
Reference
Signal Description
D2 TXD This LED indicates activity on the line
D3 RXD This LED indicates activity on the line
D4 XA-TXD This LED indicates activity on the line
D7 XA-RXD This LED indicates activity on the line