EPXA1 Development Board Hardware Reference Manual August 2002 Version 1.0 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com MNL-EPXA1DEVBD-1.
EPXA1 Development Board Hardware Reference Manual Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders.
About this Manual This manual provides comprehensive information about the Altera® EPXA1 development board. Table 1 shows the manual revision history. Table 1. Revision History Date August 2002 How to Find Information ■ ■ ■ ■ Altera Corporation Description First publication The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box. Bookmarks serve as an additional table of contents.
About this Manual How to Contact Altera EPXA1 Development Board Hardware Reference Manual For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com. For technical support on this product, go to http://www.altera.com/mysupport. For additional information about Altera products, consult the sources shown in Table 2. Table 2. How to Contact Altera Information Type Technical support USA & Canada All Other Locations http://www.altera.
EPXA1 Development Board Hardware Reference Manual Typographic Conventions About this Manual The EPXA1 Development Board Hardware Reference Manual uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.
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Contents About this Manual ..................................................................................iii How to Find Information ............................................................................................................iii How to Contact Altera .................................................................................................................. iv Typographic Conventions ..................................................................................................
Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual Anti-Static Handling ..............................................................................................................48 Power Consumption ..............................................................................................................48 Test Core Functionality .........................................................................................................49 Environmental Requirements ................
EPXA1 Development Board 1 ■ ■ ■ ■ ■ ■ ■ ■ Functional Overview Altera Corporation Powerful development board for embedded processor FPGA designs – Features an EPXA1F484 device – Supports intellectual property-based (IP-based) designs using a microprocessor Industry-standard interconnections – 10/100 megabits per second (Mbps) Ethernet – Two RS-232 ports Memory subsystem – 8 Mbytes of flash memory – 32 Mbytes of single data rate (SDR) SDRAM Multiple clocks for communications system design Multiple
EPXA1 Development Board Hardware Reference Manual EPXA1 Development Board Components This section describes the components on the EPXA1 development board, which is shown in Figure 1. Figure 1. EPXA1 Development Board Layout EPXA1 Device The EPXA1 development board features the lowest-cost member of the Excalibur family, the EPXA1. The EPXA1 device contains an ARM922T™ 32-bit RISC microprocessor combined with an APEX™ 20KE FPGA in a 484-pin FineLine BGA™ package.
EPXA1 Development Board Hardware Reference Manual In addition, the EPXA1 device provides a variety of peripherals, as listed in Table 2. Table 2.
EPXA1 Development Board Hardware Reference Manual Figure 2. Prototyping Area on the EPXA1 Development Board A1 Figure 3 on page 13 shows how the pins are located in the prototyping area.
EPXA1 Development Board Hardware Reference Manual Figure 3. Pin Layout in the Prototyping Area A PROTOIO_n B 5V C D NC E 3.3 V F GND G H J K L M N P RESET_n R 1 2 3 4 5 6 See Table 37 on page 46 for details of the prototyping area pin-outs. Interfaces Table 3 lists the interfaces supported by the EPXA1 development board. Table 3.
EPXA1 Development Board Hardware Reference Manual Serial I/O Interfaces There can be two UARTs in the EPXA1 device. A dedicated UART is located in the embedded stripe; optionally, an additional IP UART can be implemented in the FPGA. If the IP UART is used, it is connected to 3.3-V standard EPXA1 I/O pins. Each UART is connected to a transceiver (U6 for the embedded stripe UART and U1 for the IP UART) to translate LVTTL voltage for RS-232 compatibility at up to 250 Kbps.
EPXA1 Development Board Hardware Reference Manual 10/100 Ethernet Parallel Interface On the EPXA1 development board, the Ethernet interface consists of an integrated MAC/PHY device and an RJ45 connector which includes the transformer and LEDs. Table 6 lists the LEDs built into the RJ45 connector. Table 6. Ethernet LEDs Board Reference Signal Description RJ1 LEDA LEDA Green LED.
EPXA1 Development Board Hardware Reference Manual Figure 4. EPXA1 Development Board On-Board Memory Flash memory (pin 1s indicated) SDRAM (pin 1 indicated) Two flash memory chips, FLASH1 and FLASH2, are connected to the EBI of the EPXA1 development board (see Figure 5). Figure 5.
EPXA1 Development Board Hardware Reference Manual LED & Switch Interfaces The EPXA1 development board provides a variety of LED and switch interfaces. Some are user-definable and some are function-specific. Figure 6 shows the location of LEDs and switches on the development board. Figure 6.
EPXA1 Development Board Hardware Reference Manual Table 8. DG1 LED Interface Characteristics LED Reference EPXA1 I/O Pin Signal Voltage (V) W17 USER_LED9 3.3 DG1_J DG1_I W18 USER_LED8 3.3 DG1_H W20 USER_LED7 3.3 DG1_G W21 USER_LED6 3.3 DG1_F W22 USER_LED5 3.3 DG1_E Y17 USER_LED4 3.3 DG1_D Y18 USER_LED3 3.3 DG1_C Y19 USER_LED2 3.3 DG1_B Y20 USER_LED1 3.3 DG1_A Y21 USER_LED0 3.
EPXA1 Development Board Hardware Reference Manual Switch Interfaces The EPXA1 development board provides eight user-definable, active-low switches in a dip-switch block, four debounced push-button switches, and two dedicated reset switches. Table 10 documents the interface characteristics of the dip-switch block, SW6. Table 10. SW6 Dip Switch Connections (Active-Low) Switch Name EPXA1 I/O Pin Signal Voltage (V) SW6_1 V20 USER_SW7 3.3 SW6_2 V19 USER_SW6 3.3 SW6_3 V18 USER_SW5 3.
EPXA1 Development Board Hardware Reference Manual Development Board Expansion The EPXA1 development board hosts the EPXA1 device and two 5-V expansion headers, which are implemented on the board for use with expansion cards. There are two types of expansion header on the EPXA1 development board: ■ ■ Standard expansion header—a set of three 0.1-inch, two-row header pins (7 × 2, 10 × 2, 20 × 2) Long expansion header—the same set of three 0.
EPXA1 Development Board Hardware Reference Manual The expansion headers are on a common 0.1-inch pitch/spacing to make it easier to use both headers together if desired.
EPXA1 Development Board Hardware Reference Manual Difference Between Standard and Long Expansion Headers On the standard expansion header, there is an RC-filtered connection to EPXA1 device I/O pin AB5 from header pin J11.3. This circuit is suitable for producing a high-impedance, low-precision analog output if the appropriate pin is driven with a duty-cycle-modulated waveform by user logic. However, there is no RC-filtered connection to an EPXA1 device I/O pin from the long expansion header.
EPXA1 Development Board Hardware Reference Manual See Table 25 on page 35 for long expansion header pin-out details. f Jumper Configuration Refer to the Nios Embedded Processor Development Board data sheet for further details about the expansion header interface. The jumpers on the EPXA1 development board serve several functions: ■ ■ ■ Clock distribution Enabling clocks JTAG configuration Figure 8 on page 23 shows the location of jumpers on the development board. Figure 8.
EPXA1 Development Board Hardware Reference Manual Table 15.
EPXA1 Development Board Hardware Reference Manual The only device for which you cannot change the clock input is the Ethernet. The Ethernet clock input is the 25-MHz oscillator, X1. Apart from selecting the clock inputs, you can also select the target devices for each clock input. If you plug in an alternative crystal oscillator, it drives the same clock line as the SMA connector. To drive a clock through the SMA connector, you must remove the alternative crystal oscillator.
EPXA1 Development Board Hardware Reference Manual Table 16. EPXA1 Development Board Clocks (Part 2 of 2) Clock Source CLKLK_FB2p EPXA1 Pin Signal Name (or Board Connection) N21 CLKLK_FB2p Description Target Device Dedicated pin that allows external feedback to PLL2. Available on test pad T14 (see Table 36 on page 45) EPXA1 Note: (1) See “Jumper Configuration for the Clock Inputs” for details of selecting a source for the stripe CLK_REF pin.
EPXA1 Development Board Hardware Reference Manual By selecting the position of jumpers CLKA Select and CLKB Select, as shown in Table 17, either the SMA connector or an alternative 5-V DIL14 oscillator can be used instead of the 25-MHz on-board oscillator. To use the SMA connector to drive a clock onto the board from an external source, the alternative 5-V DIL14 oscillator socket must not contain an oscillator.
EPXA1 Development Board Hardware Reference Manual Using the Alternative 5-V DIL14 Oscillator To use the alternative oscillator as the stripe clock reference, follow the steps below: 1. Remove any external clock input from the SMA connector. 2. Plug the DIL14 crystal oscillator package into XSKT1. 3. Set CLKA Select to position 2-3. The clock buffer converts the 5-V input from the alternative 5-V DIL14 oscillator to the 3.3 V required for the stripe.
EPXA1 Development Board Hardware Reference Manual f For further details about booting the device from flash memory, refer to the Excalibur Devices Hardware Reference Manual. Using the Quartus II Software The Quartus II software can generate an SRAM object file (.sof) containing both hardware and software. The Quartus II programmer uses the .sof file to configure the EPXA1 device via JTAG, using either the MasterBlaster or ByteBlasterMV download cables.
EPXA1 Development Board Hardware Reference Manual The JTAG connector can be used with both the flash programmer and the Quartus programmer. In addition, the MasterBlaster and ByteBlasterMV cables support in-circuit debugging on the JTAG connector, using the SignalTap® embedded logic analyzer. The JSELECT setting does not affect this. The JSELECT jumper, J5, determines whether a JTAG debugger can be connected to the JTAG connector or to the Multi-ICE connector.
EPXA1 Development Board Hardware Reference Manual A voltage regulator regulates the main supplies for the board. The input supply is unregulated 12 V (±5%), which is reduced to 3.3 V for the I/O pins and to 1.8 V for the processor core. Voltage regulator U5 reduces the input to 5 V and distributes it to a pin on the expansion headers. The unregulated input is also routed to a pin on the expansion headers. The maximum current permitted on the expansion headers depends on the input voltage: for 3.
EPXA1 Development Board Hardware Reference Manual Table 21. 3.3-V Supply Requirements Module Max mA EPXA1 I/O 500 (sum over all I/O pins) SDRAM 285 Flash memory 45 × 2 = 90 UARTs 20 Ethernet 140 LEDs 15 × 18 + (5 × 2) Crystal oscillator = = = 270 10 280 10 Clock buffers 37 + 22 = 59 Expansion headers 500 per header Table 22. 1.8-V Supply Requirements Module EPXA1 device core Test Points & Test Pads mA Depends on application (1.
EPXA1 Development Board Hardware Reference Manual Signals Tables 23 through 27 document the device signals for the following peripherals: ■ ■ ■ UART Expansion headers Configuration/debugging interfaces UART Figure 12 shows the DB9 male connector used on the development board. Figure 12. UART DB9 Male Connector 1 2 6 4 3 7 8 5 9 Table 23 lists the UART DB9 signals. Table 23.
EPXA1 Development Board Hardware Reference Manual Expansion Headers On the development board, there is a standard expansion header and a wide expansion header. Table 24 lists the signals on the standard expansion header. Table 24.
EPXA1 Development Board Hardware Reference Manual Table 25 lists the signals on the long expansion header. Table 25.
EPXA1 Development Board Hardware Reference Manual Table 25.
EPXA1 Development Board Hardware Reference Manual Configuration/Debugging Interfaces On the development board, there are interfaces for a MasterBlaster or ByteBlasterMV cable, and a Multi-ICE connector. Table 26 lists the signals on the MasterBlaster/ByteBlasterMV connector. Table 27 lists the signals on the Multi-ICE connector. Table 28 on page 39 lists pin-out information for the development board configuration and debugging interfaces. Table 26.
EPXA1 Development Board Hardware Reference Manual Table 27. Multi-ICE Connector Signals (Part 2 of 2) Pin Signal 15 NSRST Development Board Pin-Outs Description Warm reset Direction I/O 16 GND Ground N/A 17 NC No connection N/A 18 GND Ground N/A 19 NC No connection N/A 20 GND Ground N/A The main component of the EPXA1 development board is the EPXA1F484 device. The pins on the EPXA1 device are assigned to functions on the board.
EPXA1 Development Board Hardware Reference Manual Configuration The EPXA1 device pins listed in Table 28 on page 39 are used exclusively for configuring the device. Refer to “Device Configuration” on page 28 for more information about EPXA1 configuration. Table 28.
EPXA1 Development Board Hardware Reference Manual Table 28. EPXA1 Device Configuration Pins (Part 2 of 2) Signal Name EPXA1 Device Pin Board Reference Description DEV_OE U16 Device output enable. GPIO nWS M21 Write strobe. GPIO nRS P16 Read strobe. GPIO nCS N20 Signal providing handshaking between devices. GPIO CS P17 Chip select. GPIO RDYnBSY K4 Ready/busy. GPIO CLKUSR L7 Clock signal.
EPXA1 Development Board Hardware Reference Manual Table 30 lists the SDRAM data and address bus pin-outs. Table 30. SDR SDRAM Data Bank & Address Bus Pin-Outs Signal Name SD_DQ0 EPXA1 Device Pin Board Reference B20 U13.2 Signal Name EPXA1 Device Pin Board Reference SD_DQ1 C20 U13.4 SD_DQ2 F18 U13.5 SD_DQ3 C21 U13.7 SD_DQ4 E20 U13.8 SD_DQ5 F19 U13.10 SD_DQ6 F20 U13.11 SD_DQ7 G18 U13.13 SD_DQ8 H19 U13.42 SD_DQ9 G20 U13.44 SD_DQ10 E22 U13.45 SD_DQ11 H18 U13.
EPXA1 Development Board Hardware Reference Manual EBI The EBI shares addresses and data with the flash and Ethernet MAC/PHY devices. Each device has separate chip-select lines. Table 31 shows the EPXA1 pin-outs for the EBI control signals and the board references for the flash memory and Ethernet. Table 31. EBI Control Signal Pin-Outs Signal Name EPXA1 Device Pin Ethernet Board Reference Flash Memory Board Reference Description EBI_BE0 D1 U9.96 EBI_BE1 H9 U9.97 Byte enable EBI_OE_N D2 U9.
EPXA1 Development Board Hardware Reference Manual Table 32. EBI Data Bank and Address Bus Pin-Outs (Part 2 of 2) Signal Name EPXA1 Device Pin Ethernet Board Reference Flash Memory 1 Board Reference Flash Memory 2 Board Reference EBI_DQ10 C11 U9.76 FLASH1.34 FLASH2.34 EBI_DQ11 B11 U9.75 FLASH1.36 FLASH2.36 EBI_DQ12 F12 U9.73 FLASH1.39 FLASH2.39 EBI_DQ13 A12 U9.72 FLASH1.41 FLASH2.41 EBI_DQ14 E12 U9.71 FLASH1.43 FLASH2.43 EBI_DQ15 B12 U9.70 FLASH1.45 FLASH2.
EPXA1 Development Board Hardware Reference Manual UART1 & UART2 Table 33 details the pins used for UARTs 1 and 2. Table 33. UARTs 1 & 2 I/O Pin-Outs FPGA UART EPXA1 I/O Pin Connector Pin K4 P1.4 Embedded Stripe UART Device Signal DTR EPXA1 Device Pin E6 Connector Pin P2.4 Device Signal XA_DTR J1 P1.3 TXD G5 P2.3 XA_TXD K5 P1.2 RXD F2 P2.2 XA_RXD L5 P1.6 DSR G4 P2.6 XA_DSR K3 P1.7 RTS E2 P2.7 XA_RTS L7 P1.9 RI F3 P2.9 XA_RI L6 P1.1 DCD F6 P2.1 XA_DCD L4 P1.
EPXA1 Development Board Hardware Reference Manual Test Points Table 35 on page 45 lists the test points on the EPXA1 development board. Table 35. EPXA1 Development Board Test Points Test Point Connected To Test Point Connected To TP1 GND TP6 1V8 TP2 GND TP7 GND TP3 EBI_CLK TP8 GND TP4 GND TP9 5V TP5 3V3 TP10 GND Test Pads Table 36 lists the test pads on the EPXA1 development board. Table 36.
EPXA1 Development Board Hardware Reference Manual Prototyping Area Table 36 lists the pin assignments for the prototyping area on the EPXA1 development board. Table 37.
EPXA1 Development Board Hardware Reference Manual Expansion Header I/O Pins Tables 39 and 38 list the remaining I/O pins on the standard expansion header and long expansion header, respectively, and their connections on the EPXA1 device. Table 38. Development Board Long Expansion Header (Header 1) I/O Pin-Outs Board Connector J2.3 EPXA1 Device Board Connector EPXA1 Device Board Connector EPXA1 Device W3 J2.32 N3 J9.9 Y4 J2.4 R1 J2.33 R7 J9.10 Y3 J2.5 W2 J2.34 N2 J9.11 Y2 J2.
EPXA1 Development Board Hardware Reference Manual Table 39. Development Board Standard Expansion Header (Header 2) I/O Pin-Outs Board Connector EPXA1 Device Board Connector J15.6 EPXA1 Device Y14 Board Connector J15.23 EPXA1 Device J11.4 AA14 T15 J11.5 AA12 J15.7 Y13 J15.25 T14 J11.6 AB4 J15.8 Y12 J15.27 T13 J11.7 AA10 J15.9 W16 J15.28 T12 J11.8 AA9 J15.10 W15 J15.29 R13 J11.9 AA8 J15.11 W14 J15.31 AB17 J11.10 AA7 J15.12 W13 J15.32 AB16 J11.11 AA6 J15.
EPXA1 Development Board Hardware Reference Manual Test Core Functionality The EPXA1 board is supplied with a diagnostic software image directly programmed into flash memory. When the embedded processor boots, it configures the FPGA and runs the software using the test FPGA image. The software is controlled using a serial terminal connected to the board connector, P2, and the following PC communications port settings: baud rate 38400, 8 data bits, no parity, one stop bit and no flow control.
EPXA1 Development Board Hardware Reference Manual Environmental Requirements The development board must be stored between –40 °C and 100 °C. Operating Requirements Operating temperatures must be between 0 °C and 55 °C. Unused I/O Pins Damage could result to the EPXA1 device, if all unused I/O pins are not set to tri-state mode in the Quartus II software. To set the unused I/O pins to tri-state mode, run the Quartus II software, open the appropriate project, and follow the steps below: 50 1.
