Specifications

Altera Corporation 59
EPXA10 Development Board Hardware Reference Manual
SDR SDRAM Interface
The SDRAM module is 64 bits wide, and the general-purpose memory
data bus is 32 bits wide. To allow access to the entire SDRAM memory
array, data bus pins are doubled. This means that the upper half of the
data bus is connected to the lower half. For example, GPM_D(0) is
connected to data pin 0 and data pin 32 on the SDRAM DIMM. Ensure that
only 32 bits of the SDRAM data bus are enabled at a time (D[31..0] or
D[63..32]) to avoid contention.
The SDRAM_DQM[7:0] lines are used to enable the SDRAM outputs.
Because the data bus pins are doubled-up on the SDRAM DIMM, both
halves of the data bus may not be enabled at the same time. For example,
if SDRAM_DQM[0] is enabled, SDRAM_DQM(4) cannot be enabled or
contention will occur.
Table 47 shows the pin-outs for the SDR SDRAM control signals.
Table 47. SDR SDRAM Control Signal Pin-Outs
Signal Name EPXA10 Device Pin Description
SD_RAS_N F17 Row address strobe
SD_CAS_N F18 Column address strobe
SD_WE_N G18 Write enable
SD_CS0_N G14 Chip select
SD_CS1_N F16 Chip select
SD_CLKE F14 Clock enable
SD_CLK F15 SDRAM clock
SD_CLK_N G13 SDRAM clock - inverted
SD_DQM(0) H14 Data byte mask
SD_DQM(1) L14 Data byte mask
SD_DQM(2) K9 Data byte mask
SD_DQM(3) H9 Data byte mask
SD_DQS(0) J14 DQS signal
SD_DQS(1) K14 DQS signal
SD_DQS(2) K10 DQS signal
SD_DQS(3) H10 DQS signal