Specifications

58 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
Table 46. EPXA10 Device Configuration Pins
Signal Name EPXA10 Device Pin Description
MSEL0 J30 Configuration mode select (tied to GND)
MSEL1 K30 Configuration mode select (tied to GND)
NSTATUS AM14 OE for EPC2s
NCONFIG R30 INIT for EPC2s
DCLK W3 Data clock for EPC2s
CONF_DONE AM13 Configuration complete indicator
INIT_DONE D14 Initialization complete indicator
nCE AC3 Not connected
nCEO D13
DATA0 V3 Serial input for EPC2 configuration data
DATA1 D10 Serial input for EPC2 configuration data; available for user I/O after
configuration
DATA2 A9
DATA3 B9
DATA4 C9
DATA5 D9
DATA6 A4
DATA7 B4
TDI AD3 JTAG data input
TDO E11 JTAG data output (to next device in the chain
TCK AM19 JTAG clock
TMS AM20 JTAG mode select
TRST C13 JTAG reset (pulled high)
PROC_TDI H27 JTAG data input
PROC_TDO H26 JTAG data output (to next device in the chain
PROC_TCK D30 JTAG clock
PROC_TMS E29 JTAG mode select
PROC_TRST E30 JTAG reset (pulled high)
DEV_CLRn H3 Global reset for the device
DEV_OE AE3 Device output enable
nWS C4 Write strobe
nRS D4 Read strobe
nCS D3 Signal providing handshaking between devices
CS E3 Chip select
RDYnBSY E14 Ready/busy
CLKUSR A13 Clock signal