Specifications

Altera Corporation 57
EPXA10 Development Board Hardware Reference Manual
Development
Board Pin-Outs
& Signals
The main component of the development board is the EPXA10F1020C2
device. The pins on the EPXA10 device are assigned to functions on the
board. When generating IP cores for the EPXA10 device, the pins must be
used as defined to avoid damaging the device. The following sections list
the interfaces and dedicated pins on the board. Any pins not used for a
design should be left in the high-impedance (input) state to avoid
contention.
This section details the pins on the EPXA10 device which are assigned to
the following purposes:
■ Configuration
■ SDR SDRAM
■ EBI
■ UARTs 1 and 2
■ Ethernet
■ User LEDs, push buttons, and dip-switches
■ Fast I/O pins
■ Test points.
Pin assignments are grouped into tables for control pins, bank address
pins, and data bus pins where appropriate. The tables also detail signals
passing across a connection. The remaining I/O pins on the EPXA10
device are listed at the end of this section.
Configuration
The EPXA10 device pins listed in Table 46 on page 58 are used exclusively
for configuring the device. Refer to “General Information” on page 17 for
more information about EPXA10 configuration.
 Refer to the ARM-Based Embedded Processor PLDs Hardware
Reference Manual for details of the power pins.
17 N.C. No connection N/A
18 GND Ground N/A
19 NA No connection N/A
20 GND Ground N/A
Table 45. Multi-ICE Connector (Part 2 of 2)
Pin Signal Description Direction