Specifications

56 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
Table 44 lists the pin assignments on the MasterBlaster/ByteBlasterMV
connector.
Table 45 lists the pin assignments on the Multi-ICE connector.
Table 44. MasterBlaster/ByteBlasterMV Female Connector
Pin JTAG Mode
Signal Description
1 TCK Clock signal
2 GND Signal ground
3 TDO Data from device
4 VCC Power supply
5 TMS JTAG state machine control
6 VIO Reference voltage for MasterBlaster/ByteBlasterMV output
driver
7 TCK Clock signal
8 - No connection
9 TDI Data to device
10 GND Signal ground
Table 45. Multi-ICE Connector (Part 1 of 2)
Pin Signal Description Direction
1 VCC Power supply N/A
2 VCC Power supply N/A
3 PROC_NTRTST Processor reset O
4 GND Ground N/A
5 PROC_TDI Processor test data input I
6 GND Ground N/A
7 PROC_TMS Processor test mode select I
8 GND Ground N/A
9 PROC_TCK Processor test clock input I
10 GND Ground N/A
11 GND Ground N/A
12 GND Ground N/A
13 PROC_TDO Processor test data output O
14 GND Ground N/A
15 NSRST Warm reset I/O
16 GND Ground N/A