Specifications

Altera Corporation 55
EPXA10 Development Board Hardware Reference Manual
Note:
(1) Board revision 1 only.
Table 43. MICTOR Connector: JTAG, Clocks & I/O
Pin Signal Description Pin Signal Description
1 N.C. 2 N.C.
3 N.C. 4 N.C.
5 PROC_TDO JTAG data output (to next
device in the chain
6 SD_DQ_ECC6 Standard I/O (not
used)
7 PROC_TDI JTAG data input 8 SD_DQ_ECC5
9 PROC_TCK JTAG clock 10 SD_DQ_ECC4
11 PROC_TMS JTAG mode select 12 SD_DQ_ECC3
13 PROC_NTRST JTAG reset (pulled high) 14 SD_DQ_ECC2
15 TDO JTAG data output (to next
device in the chain
16 SD_DQ_ECC1
17 TDI JTAG data input 18 SD_DQ_ECC0
19 TCK JTAG clock 20 NCLK3(1) Clock
21 TMS JTAG mode select 22 NCLK2(1)
23 nPOR 24 NCLK1_FB(1)
25 CLK_REF 26 CLK0_FBp(1)
27 CLK0 28 CLK1_FBp(1)
29 CLK1 30 CLK0_OUT(1)
31 CLK2 32 CLK1_OUT(1)
33 CLK3 34 NCLK1(1)
35 36 NCLK0_FB(1)
37 38 NCLK0(1)
39 GND Ground 40 GND Ground
41 GND Ground 42 GND Ground
43 GND Ground