Specifications

Altera Corporation 41
EPXA10 Development Board Hardware Reference Manual
Test &
Debugging
Features
The development board includes the following test features:
■ JTAG connectors for use with either the MasterBlaster or
ByteBlasterMV, or Multi-ICE
■ Test connectors provided for debugging with a logic analyzer
■ Matched impedance connectors (MICTORs), which can be used for
debugging the individual interfaces
JTAG Programming Chain
There are two JTAG connectors on the EPXA10 development board. Each
is connected to a JTAG chain. The MasterBlaster/ByteBlasterMV
connector is connected to JTAG and is used to configure the PLD using
ByteBlasterMV or MasterBlaster; and the Multi-ICE is connected to
JTAG_PROC.
All devices that can be programmed through the JTAG interface are
connected to a MasterBlaster/ByteBlasterMV-type connector. The devices
connected to the chain are programmed in the following order:
■ EPXA10 device
■ EPC2 configuration devices
■ PCI interface
You can use both JTAG connectors at the same time. A 2 x 5 header, which
is used for configuration by the MasterBlaster or ByteBlasterMV, is
connected to JTAG. The other JTAG connector is a 2 x 10 header connected
to PROC_JTAG, which can only be used by Multi-ICE. The jumper
JSELECT is used to specify whether the MasterBlaster/ByteBlasterMV is
used in parallel with the Multi-ICE, or alone.
Configuring the JTAG Chain
You can configure the EPXA10 JTAG chain by setting the JSELECT jumper
and using the appropriate jumper settings to bypass devices not required
in the programming chain.
If a device is not included in the programming chain, it must be bypassed
to prevent the JTAG chain from being broken. Jumpers JP50 and JP57
determine bypass settings for the EPC2 configuration devices, as shown
in Table 31 on page 42.