Specifications

Altera Corporation 39
EPXA10 Development Board Hardware Reference Manual
Note:
(1) See “Jumper Configuration for the Clock Input” for details of selecting a source for the stripe clock reference.
(2) Test point.
The clocks on the development board can be configured as required,
depending on which devices are used; refer to “Clock Generation &
Distribution” on page 19 for a comprehensive list of potential clock
requirements.
Jumper Configuration for the Clock Input
Jumpers JP31, JP32, JP40, JP41, and JP51 through JP55 are used to select
different clock inputs:.
■ JP31 and JP32 can be used to connect CLK3 to lvdstxinclk1p and
NCLK3 to lvdstxclk1n, respectively
■ JP40 is used to set CLK0 to oscillator 0 (position 1-2) or TX_CLK
(position 2-3) and JP41 is used to set CLK1 to oscillator 1 (position 1-
2) or RX_CLK (position 2-3)
■ JP51to JP55 enable and disable the clocks (X7 to X11, respectively)
During development, if you need to run the clock at a slower rate, you can
do so using either the external clock input or a variable oscillator.
The external oscillator is a BNC cable input (J4) that can be used to input
a signal from a laboratory signal generator. The variable oscillator is a
four-pin socket that supports a variety of 5-V oscillators.
CLKLK_FB1p AL28 CLK0_FBp Dedicated pin that allows external
feedback to the PLL
U125.197 CLK0_FBp
CLKLK_FB2p K3 TP_CLK1_FBp Dedicated pin that allows external
feedback to the PLL
U125.95 CLK1_FBp
Table 30. EPXA10 Development Board Clock Sources (Part 2 of 2)
EPXA10 Pin
Name
EPXA10
Pin
Number
Connection To Description Expansion
Connector
Board Name
Connection