Specifications
38 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
Clock
Distribution
Dedicated inputs on the EPXA10 device are used for clocks. Five are zero-
skew; four are global inputs to the PLD and one is a dedicated input
providing the embedded processor stripe reference clock. The four PLD
clocks service the ClockLock
™
and ClockBoost
™
circuitry on the Excalibur
device. Table 30 lists all the clock sources on the development board.
Table 30. EPXA10 Development Board Clock Sources (Part 1 of 2)
EPXA10 Pin
Name
EPXA10
Pin
Number
Connection To Description Expansion
Connector
Board Name
Connection
CLK_REF A28 X7/U147/
J4 (1)
50-MHz main clock provided to the
synchronous memory and embedded
processor. Dedicated input
CLK_REF
CLK1p N30 X8 Dedicated pin that drives
32.768_MHz clock and inputs
CLK0
CLK2p Y3 X9 Dedicated pin that drives
32.768_MHz clock and inputs
CLK1
CLK3p W30 X10 Dedicated pin that drives
32.768_MHz clock and inputs
CLK2
CLK4p P3 X11 Dedicated pin that drives
32.768_MHz clock and inputs
CLK3
CLK1n V30 TP_NCLK0(2) Dedicated pin that drives clock and
inputs in LVDS mode
U125.199 NCLK0
CLK2n R3 NCLK1(2) Dedicated pin that drives clock and
inputs in LVDS mode
U125.97 NCLK1
CLK3n Y30 NCLK2(2) Dedicated pin that drives clock and
inputs in LVDS mode
U125.87 NCLK2
CLK4n N3 NCLK3(2) Dedicated pin that drives clock and
inputs in LVDS mode
U125.89 NCLK3
CLKLK_FB1N0 AM28 TP_NCLK0FB(2) Dedicated pin that allows external
feedback to the PLL in LVDS mode
U125.195 NCLK0_FB
CLKLK_FB2N0 J3 TP_NCLK1FB(2) Dedicated pin that allows external
feedback to the PLL in LVDS mode
U125.93 NCLK1_FB
LOCK1 AC30 N/A Status of ClockLock PLL1 U126.83 AC30
LOCK2 AK4 N/A Status of ClockLock PLL2 U126.8 AK4
LOCK3 H30 N/A Status of ClockLock PLL3 U126.85 H30
LOCK4 AK5 N/A Status of ClockLock PLL4 U126.3 AK5
CLKLK_ENA P30 N/A Dedicated pin used for PLL circuitry PLLENABL
CLKLK_OUT1p AM29 CLK0_OUT Dedicated pin that allows the PLL
output to be driven off-chip
U125.99 CLK0_OUT
CLKLK_OUT2p AH3 TP_CLK1_OUT Dedicated pin that allows the PLL
output to be driven off-chip
U125.91 CLK1_OUT