Specifications

36 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
Note:
(1) Connects SDRAM DQS0 to SD_CLK_n.
(2) Connects the trace port signals to either JTAG or PROC_JTAG.
(3) Connects the device to the PCI JTAG.
(4) Used to select configuration mode. See “Configuration Interfaces” on page 22.
(5) Connects PLD clock 3 for LVDS. See AN 115: Using the ClockLock and ClockBoost PLL Features in APEX Devices.
(6) Matching load for the embedded processor stripe clock.
(7) Determines whether serial or dual JTAG chains are used for debugging.
(8) Enables/disables debugging.
(9) Connects PLD clocks 0 or 1 to the Ethernet clock.
(10) Enables/disables the Ethernet clock.
(11) Enables/disables clocks.
(12) Set to position 1-2.
Figure 10 on page 37 shows the development board jumper configuration.
MSEL1 (4) MSEL1 (0) MSEL1 (1) 1-2
JP31 (5) CLK3->LVDSTXINCLK1p - None
JP32 (5) nCLK3->LVDSTXINCLK1n - None
JP33 (6) CLK_REF 50 Ohms
N/A
None
JSELECT (7) JSELECT=0 JSELECT=1 1-2
DEBUG_EN (8) DEBUG_EN=0 DEBUG_EN=1 2-3
BOOT_FLASH (4) BOOT_FLASH=0 BOOT_FLASH=1 2-3
EN_SELECT (not connected) EN_SELECT=0 EN_SELECT=1 None
JP40 (9) CLK0=Ext_Osc0 CLK0=TX_CLK 1-2
JP41 (9) CLK1=Ext_Osc1 CLK1=RX_CLK 1-2
JP_VPP VPP=12 V VPP=3.3 V 2-3
U179 (10) PHY 25MHz Clock Disabled PHY 25MHz Clock Enabled 2-3
JP50 (see Table 31 on page 42)OFF—not to be used - 1-2
JP51 (11) X7 Osc Disabled X7 Osc Enabled 2-3
JP52 (11) X8 Osc Disabled X8 Osc Enabled 2-3
JP53 (11) X9 Osc Disabled X9 Osc Enabled 2-3
JP54 (11) X10 Osc Disabled X10 Osc Enabled 2-3
JP55 (11) X11 Osc Disabled X11 Osc Enabled 2-3
JP57 (see Table 31 on page 42)ECP2 Bypass - 1-2
JP58 (12) 3.3 V 2.5 V 1-2
JP59 (12) 3.3 V 2.5 V 1-2
JP_AGND2GND Analog to digital GND - 1-2
JP_PSU_SDR OFF—not to be used - None
Table 29. Jumpers (Part 2 of 2)
Jumper & Description Pins 1-2 Connected Pins 2-3 Connected Default