Specifications

Altera Corporation 35
EPXA10 Development Board Hardware Reference Manual
Jumper
Configuration
The jumpers on the EPXA10 development board serve several functions:
■ Clock distribution
■ Enabling clocks
■ JTAG configuration
■ Enabling the PLL interface
Table 29 lists the jumpers on the EPXA10 development board.
Table 27. Push-Button Switches
Push Button
Reference
Use Connected To
SW_RESET Generates a warm reset nCONFIG
SW_DEV_CLR_N Resets the PLD DEV_CLR_n
SW6 Generates an interrupt on the EBI interface when enabled by
the interrupt controller; otherwise connected to user-defined I/O
U10 and G25
Table 28. User-Definable Push-Button Switches
Push Button Reference I/O Pins Voltage
SW3 T8 3.3 V
SW4 R5 3.3 V
SW5 U4 3.3 V
SW6 U10 3.3 V
Table 29. Jumpers (Part 1 of 2)
Jumper & Description Pins 1-2 Connected Pins 2-3 Connected Default
JP1 (1) SD_DQS0_SD_CLK_N
N/A
1-2
JP2 (2) TRACE_PORT_TCK (TCK) TRACE_PORT_TCK (PROC_TCK) 2-3
JP3 (2) TRACE_PORT_TMS (TMS) TRACE_PORT_TMS (PROC_TMS) 2-3
JP4 (2) TRACE_PORT_TD0 (TD0) TRACE_PORT_TD0 (PROC_TD0) 2-3
JP5 (2) TRACE_PORT_TD1 (TD1) TRACE_PORT_TD1 (PROC_TD1) 2-3
JP6 (2) TRACE_PORT_TRST (TRST) TRACE_PORT_TRST (PROC_TRST) 2-3
JP14 (3) PCI_TDI (PCI_TDIO1)
N/A
None
JP15 (3) PCI_TCK
N/A
None
JP16 (3) PCI_TRST
N/A
None
JP17 (3) PCI_TMS
N/A
None
JP18 (3) PCI_TDI (PCI_TDO)
N/A
None
MSEL0 (4) MSEL0 (0) MSEL0 (1) 1-2