Specifications

Altera Corporation 25
EPXA10 Development Board Hardware Reference Manual
Ethernet Switches
Table 18 lists the switches used for the Ethernet device in the S2 switch
bank; and Table 19 shows how the TECH switches are used to set the
Ethernet decoding protocol.
PCI Interface
Two PCI slots are implemented on the board. The 32-bit interface is
capable of 33 MHz and operates at 3.3 V; it complies with PCI Local Bus
Specification, Revision 2.2. The slots can be used with 3.3-V and universal
PCI cards.
User I/O pins are provided for this interface. Table 37 on page 49 lists the
PCI signal pin assignments.
Table 18. S2 Switches for PHY
Identifier Switch Dip-Switch for Ethernet PHY
ANEGA 1 Auto-negotiation enable
TECH0 2
Used to specify the Ethernet decoding
TECH1 3
TECH2 4
PHYAD0 5
Physical Address
PHYAD1 6
PHYAD2 7
PHYAD3 8
PHYAD4 9
Table 19. Ethernet Protocol Decoding
TECH [2:0] Function
000
Advertise no technology capability
111
Both 10-BASE T and 100-BASE T
001
10-BASE T, half duplex
010
100-BASE T, half duplex
011
Both 10-BASE T and 100-BASE T, half duplex
100
None
101
10-BASE T, full/half duplex
110
100-BASE T, full/half duplex