Specifications

22 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
To configure the device using the EPC2 devices, start the Quartus II
software, and specify the EPC2 device as an output option to create the
required .pof files. If the EPC2 devices are not specified, the Quartus II
software generates a single file to program the EPXA10 device directly.
Configuration Interfaces
Table 12 shows the data sources for configuration that are available for the
EPXA10 device.
EPC2 Device Configuration
The EPC2 device section consists of eight EPC2 devices, which are a part
of the on-board JTAG chain, to allow in-system programming.
The EPC2 devices contain reprogrammable flash memory to configure the
embedded-processor PLD serially. For more details about configuring
these devices, refer to the data sheet Configuration Devices for ACEX,
APEX, FLEX & Mercury Devices.
MasterBlaster/ByteBlasterMV Communications Cable
These cables have a 10-pin header for use with the development board.
The cable allows you to download hardware and software configuration
data directly to the EPXA10 device or to the EPC2 configuration devices.
The development board supports only JTAG download mode, not passive
serial download mode. The MasterBlaster and ByteBlasterMV cables also
support in-circuit debugging with the SignalTap
®
embedded logic
analyzer.
Two green LEDs are provided on the MasterBlaster cable: one for use with
the CONF_DONE signal and one for use with the nSTATUS signal.
The board header supply voltage is 3.3 V.
 The MasterBlaster cable can also be used in conjunction with the
ARM debugger to debug your software using JTAG.
Table 12. Supported Configuration Schemes
Configuration Scheme Data Source
Configuration devices EPC2 configuration device
JTAG MasterBlaster/ByteBlasterMV download cable