Specifications

Altera Corporation 19
EPXA10 Development Board Hardware Reference Manual
Figure 4. Flash Memory Interface
The EPXA10 development board can be used equally well with either
Intel or the AMD flash memory.
Clock Generation & Distribution
There are five clock generators on the EPXA10 development board,
connected to crystal oscillators that can be enabled and disabled according
to your design requirements. Optionally, the Ethernet clock can be used to
drive two of the PLD clocks. The reference clock for the embedded
processor stripe (CLK_REF) uses a zero-delay clock buffer to allow a 3.3-V
to 5-V interface as well as buffering the clock signal. Refer to “Jumper
Configuration” on page 35 for more about configuring the clock options
on the development board.
The devices configured on the EPXA10 development board determine
which clocks are required. Table 9 gives a comprehensive list of the clocks,
assuming that all devices are used.
Figure 5 on page 20 shows the location of the clocks.
EPXA10
EBI
A1-A21
D0-D15
OE, WE, CE
A0-A20
Flash Memory (4 x 4 Mbyte)
3.3 V 12 V
Programming
voltage
1234
Table 9. Clock Requirements
Clock Used In Speed
CLK_REF EPXA10 stripe 50 MHz
CLK0 PLD 32.768 MHz
CLK1 PLD 32.768 MHz/tx_clk1
CLK2 PLD 32.768 MHz/rx_clk1
CLK3 PLD 32.768 MHz
CLKIN Ethernet 25 MHz