Specifications

Altera Corporation 17
EPXA10 Development Board Hardware Reference Manual
General
Information
When power is initially applied to the board, the LEDs flash according to
the software test running on the embedded processor. The test suite is
programmed directly into flash memory, and when the embedded
processor boots it configures the PLD and runs the software using the test
PLD image.
Functional
Overview
This section gives a brief overview of the EPXA10 development board
components. Figure 2 on page 12 shows a functional block diagram of the
development board.
EPXA10F1020C2 Device
The main component of the development board is the EPXA10F1020C2
device in a 1,020-pin FineLine BGA package. Table 6 lists the features of
the EPXA10 device.
User I/O pins The expansion header provides up to 502 user I/O pins that connect directly to the
EPXA10 device, supporting custom interfaces
IEEE Std. 488 RS-232
serial interfaces
This interface is a 12.0-V transceiver with 235-kbps data rate in a TSSOP package
Debugging/programming
ports
The board supports in-circuit debugging by means of the MasterBlaster,
ByteBlasterMV, or Multi-ICE cables
MICTOR connectors This connector provides debugging and monitoring facilities for the UART, EBI,
SDRAM, Trace and JTAG
Table 5. Development Board Interfaces (Part 2 of 2)
Interface Description
Table 6. EPXA10 Device Features
Feature Capacity
Maximum system gates 1,772,000
Typical gates 1,000,000
LEs 38,400
ESBs 160
Maximum RAM bits 327,680
Maximum macrocells 2,560
Maximum user I/O pins 708