Specifications

16 Altera Corporation
EPXA10 Development Board Hardware Reference Manual
Clocks
The EPXA10 embedded processor stripe has one clock input, which can be
driven from one of three sources as follows:
■ A dedicated on-board crystal oscillator
■ An alternative crystal oscillator
■ A waveform generator using a BNC connector
The EPXA10 PLD has four clock inputs, all using 32-MHz on-board crystal
oscillators.
Memory
The EPXA10 development board has the following memory:
■ Up to 512 Mbytes 32-bit SDR SDRAM (optional) can be connected via
the DIMM socket. The SDRAM interface on the EPXA10
development board is limited to 75 MHz operation
■ 16 Mbyte 16-bit flash memory (4 × 4-Mbyte blocks)
Development Board Expansion
The EPXA10 development board supports the EPXA10 device and
simultaneously supports flexible expansion:
■ Four expansion headers allow the connection of daughter boards
■ Two PCI connectors accommodate 3.3-V and universal PCI
expansion cards
Interfaces
Table 5 describes the interfaces supported by the board.
Table 5. Development Board Interfaces (Part 1 of 2)
Interface Description
PCI connectors The connectors operate at 32-bit, 33 MHz and can be used by designers to connect
standard, commercially-available 3.3-V and universal PCI cards
10/100 Ethernet with full-
and half-duplexing
This interface consists of a connector, transceiver and transformer. The MAC is
implemented in the Altera device as an IP block. The connection between the MAC
and the transceiver is a standard MII
Expansion headers These connectors allow designers to stack multiple daughter boards as required