EPXA10 Development Board Hardware Reference Manual April 2002 Version 1.1 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com MNL-EPXA10DEVBD-1.
EPXA10 Development Board Hardware Reference Manual Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders.
About this Manual This manual provides comprehensive information about the Altera® EPXA10 development board. Table 1 shows the manual revision history. Table 1. Revision History Date How to Find Information March 2002 First publication as a reference document April 2002 Change the product codes from EPXA10F1020Cx to EPXA10F1020C2 ■ ■ ■ ■ Altera Corporation Description The Adobe Acrobat Find feature allows you to search the contents of a PDF file.
About this Manual EPXA10 Development Board Hardware Reference Manual How to Contact Altera For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com. For additional information about Altera products, consult the sources shown in Table 2. Table 2.
EPXA10 Development Board Hardware Reference Manual Typographic Conventions About this Manual The EPXA10 Development Board Hardware Reference Manual uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.
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Contents Hardware Reference Manual How to Find Information ............................................................................................................iii How to Contact Altera .................................................................................................................. iv Typographic Conventions ............................................................................................................. v Features ......................................................
Contents User LEDs, Switches and Push Button LEDs .....................................................................63 List of Test Points ...................................................................................................................63 Expansion Header I/O Pins .........................................................................................................65 General Usage Guidelines ............................................................................................
EPXA10 Development Board 1 Features ■ ■ Powerful development board for embedded processor PLD designs – Features an EPXA10F1020C2 device – Supports intellectual property-based (IP-based) designs using a microprocessor Industry-standard interconnections – 10/100 megabits per second (Mbps) Ethernet with full and half duplexing – Two 3.
EPXA10 Development Board Hardware Reference Manual The EPXA10 development board provides a flexible, powerful debug and development environment. Designers can use the board for a variety of purposes, including building and emulating systems for special requirements, and conducting trace and debug investigations. Figure 1 on page 11 shows a layout diagram of the EPXA10 development board.
EPXA10 Development Board Hardware Reference Manual Figure 1.
EPXA10 Development Board Hardware Reference Manual EPXA10 Embedded Processor PLD The EPXA10F1020C2 embedded processor PLD features 1,000,000 ASICequivalent gates in a 1,020-pin FineLine BGA™ package with 38,400 logic elements and 327,680 ESB RAM bits.
EPXA10 Development Board Hardware Reference Manual Board Profile The development board comprises 14 layers, which are used as follows: ■ ■ ■ ■ 10 signal layers Full 3.3-V power plane 2 ground layers Analog ground layer The board dimensions are 11.5” × 8”. Power Supply The board includes connectors that support both laboratory bench power supplies and commercially-available, PC-style power supplies (ATX). A status LED is provided for each power supply.
EPXA10 Development Board Hardware Reference Manual Table 3. 3.3-V Supply Requirements Module mA (3.3 V) EPXA10 I/O (1) Depends on application SDRAM DIMM module 500 Flash memory 300 PCIs 7.6A (system-dependent) UARTs 50 Ethernet - LEDs 20 × 22 EPC2 50 × 8 Crystal oscillator 15 × 5 Power-on reset 10 32 × 2 Clock buffers Note: (1) Jumpers JP58 and JP59 must be set to 3.3 V Table 4. 1.8-V Supply Requirements Module EPXA10 device core mA (1.
EPXA10 Development Board Hardware Reference Manual + ATX + Figure 3. EPXA10 Power Supply Inputs 18 17 NC 3.3 V 2.5 V GND 3.3 V 1.8 V See Figure 1 on page 11 to locate this subsection on the development board. Environmental Requirements The development board must be stored between –40 °C and 100 °C. Operating Requirements Operating temperatures must fall between 0 °C and 55 °C. The development board uses commercial grade components and must be convection-cooled.
EPXA10 Development Board Hardware Reference Manual Clocks The EPXA10 embedded processor stripe has one clock input, which can be driven from one of three sources as follows: ■ ■ ■ A dedicated on-board crystal oscillator An alternative crystal oscillator A waveform generator using a BNC connector The EPXA10 PLD has four clock inputs, all using 32-MHz on-board crystal oscillators.
EPXA10 Development Board Hardware Reference Manual Table 5. Development Board Interfaces (Part 2 of 2) Interface Description User I/O pins The expansion header provides up to 502 user I/O pins that connect directly to the EPXA10 device, supporting custom interfaces IEEE Std. 488 RS-232 serial interfaces This interface is a 12.
EPXA10 Development Board Hardware Reference Manual In addition, the EPXA10 device provides a variety of on- and off-chip peripherals, as listed in Table 7. Table 7.
EPXA10 Development Board Hardware Reference Manual Figure 4. Flash Memory Interface Flash Memory (4 x 4 Mbyte) 1 EPXA10 A1-A21 2 3 4 A0-A20 D0-D15 EBI OE, WE, CE 3.3 V 12 V Programming voltage The EPXA10 development board can be used equally well with either Intel or the AMD flash memory. Clock Generation & Distribution There are five clock generators on the EPXA10 development board, connected to crystal oscillators that can be enabled and disabled according to your design requirements.
EPXA10 Development Board Hardware Reference Manual Figure 5. Clock Generators on the EPXA10 Development Board External Clock Supply PLD Clocks CLK_REF (stripe) Ethernet Clock CLK0 CLK3 CLK1 CLK2 See Figure 1 on page 11 to locate this subsection on the development board.
EPXA10 Development Board Hardware Reference Manual Table 10 shows the board jumper requirements for booting from flash memory; see “Jumper Configuration” on page 35 for more details. Table 10. Board Configuration for Booting from Flash Memory f BOOT_FLASH MSEL0 MSEL1 Mode 1 (position 2-3) 0 (position 1-2) 0 (position 1-2) Boot from 16-bit flash For further details about booting the device from flash memory, refer to the ARM-Based Embedded Processor PLDs Hardware Reference Manual.
EPXA10 Development Board Hardware Reference Manual To configure the device using the EPC2 devices, start the Quartus II software, and specify the EPC2 device as an output option to create the required .pof files. If the EPC2 devices are not specified, the Quartus II software generates a single file to program the EPXA10 device directly. Configuration Interfaces Table 12 shows the data sources for configuration that are available for the EPXA10 device. Table 12.
EPXA10 Development Board Hardware Reference Manual Serial I/O Interfaces The development board contains two RS-232 DTE interfaces. For each, the transceiver and any associated hardware are provided on the board. Table 13 provides information on the devices used to implement the RS-232 interfaces. Table 13. RS-232 Interface Device Reference Reference Part Number Manufacturer Website Address Description U35 MAX3241 Maxim www.maxim-ic.
EPXA10 Development Board Hardware Reference Manual Table 15. UART LEDs (Part 2 of 2) LED Reference Description RX_UART2 This is set on to indicate activity on the line CONF_DONE This is set on to indicate that PLD configuration is complete 10/100 Ethernet Parallel Interface The Ethernet interface consists of a transceiver, or PHY layer, and associated discrete components. You can use the interface to implement an Ethernet media access controller (MAC) in the EPXA10 device.
EPXA10 Development Board Hardware Reference Manual Ethernet Switches Table 18 lists the switches used for the Ethernet device in the S2 switch bank; and Table 19 shows how the TECH switches are used to set the Ethernet decoding protocol. Table 18. S2 Switches for PHY Identifier Switch ANEGA 1 TECH0 2 TECH1 3 TECH2 4 PHYAD0 5 PHYAD1 6 PHYAD2 7 PHYAD3 8 PHYAD4 9 Dip-Switch for Ethernet PHY Auto-negotiation enable Used to specify the Ethernet decoding Physical Address Table 19.
EPXA10 Development Board Hardware Reference Manual EPXA10 Device Signal Definitions for the PCI Card Table 20 shows the definitions for the EPXA10 device signals required to implement the PCI interface. Table 20. EPXA10 Device Signal Definitions Function Signals Number Address and data AD[31..0] C/BE[3..
EPXA10 Development Board Hardware Reference Manual Board-Level Issues The PCI interface requires no devices on the board level if the PCI is implemented as an IP core in the EPXA10 device. All of the power supplies are provided when the ATX power supply is connected on the EPXA10 development board. Table 22 lists the PCI interface characteristics. Table 22. PCI Interface Characteristics Interface Features I/O Pins PCI Interface 55 plus clock Voltages Clocks +3.
EPXA10 Development Board Hardware Reference Manual All LEDs, switches and push buttons are accessible from the expansion headers. Users can design expansion cards to their specific requirements using the I/O pins on the EPXA10 device and power supplies from the EPXA10 development board. The connectors are stackable, so more than one card can be plugged on each header, allowing users to develop different cards for individual modules within a complex design.
EPXA10 Development Board Hardware Reference Manual Figure 6. EPXA10 Development Board TOLC Expansion Header Connections U126 U125 XA1 U123 U124 The dimensions given in Figures 7 to 9 are inches, measured from the centre of the pad. Figure 7 on page 30 gives dimensions for the TOLC expansion headers categorized in Table 23 on page 27.
EPXA10 Development Board Hardware Reference Manual 1.9500 Figure 7. EPXA10 Development Board TOLC Dimensions 2.7250 3.8000 0.8700 0.6830 All dimensions are in inches. To connect to the motherboard, a daughter board must use SOLC connectors, for which dimensions are given in Figure 8 on page 31.
EPXA10 Development Board Hardware Reference Manual Figure 8. Daughter Board SOLC Dimensions 1.9400 2.7250 3.8000 0.8570 0.6690 a All dimensions are in inches. Figure 9 on page 32 is a mechanical diagram giving the position of the TOLC connectors on the motherboard layout. Altera Corporation The PCB footprints for TOLC and SOLC connectors differ.
EPXA10 Development Board Hardware Reference Manual Figure 9. Mechanical Diagram of the EPXA10 Development Board Expansion Headers X DIA. 0.132" x 4 off X Centre of U125 pin 1 PCB pad X 2.100 2.800 2.300 2.075 O O Centre of U126 pin 1 PCB pad 0.125 X 0, 0 0 X XA1 center O 1.725 O 2.800 X 2.600 2.250 X Centre of U123 pin 1 PCB pad X Centre of U124 pin 1 PCB pad 0.900 1.400 1.600 1.250 1.370 2.050 2.200 32 All dimensions are in inches.
EPXA10 Development Board Hardware Reference Manual To design a matching daughter board, designers must do one of the following: ■ ■ Base designs on the SOLC expansion header dimensions given in Figure 8 on page 31 Translate dimensions from the TOLC motherboard dimensions LED & Switch Interfaces The EPXA10 development board provides a variety of LED and switch interfaces. LED Interface The development board has eight LEDs that are used for applicationspecific functions on the EPXA10 device.
EPXA10 Development Board Hardware Reference Manual Table 26. Application LED Usage LED Reference Description –5V –5-V power supply indicator 5V 5-V power supply indicator 2.5V 2.5-V power supply indicator 12V 12-V power supply indicator 3.3V 3.3-V power supply indicator –12V –12-V power supply indicator 1.8V 1.8-V power supply indicator LEDL LED link. This is set on during linkup LEDTX LED transmit. This is set on during transmission LEDRX LED receive.
EPXA10 Development Board Hardware Reference Manual Table 27. Push-Button Switches Push Button Reference SW_RESET Use Connected To Generates a warm reset nCONFIG SW_DEV_CLR_N Resets the PLD DEV_CLR_n SW6 U10 and G25 Generates an interrupt on the EBI interface when enabled by the interrupt controller; otherwise connected to user-defined I/O Table 28. User-Definable Push-Button Switches Push Button Reference Jumper Configuration I/O Pins Voltage SW3 T8 3.3 V SW4 R5 3.3 V SW5 U4 3.
EPXA10 Development Board Hardware Reference Manual Table 29.
EPXA10 Development Board Hardware Reference Manual Figure 10.
EPXA10 Development Board Hardware Reference Manual Clock Distribution Dedicated inputs on the EPXA10 device are used for clocks. Five are zeroskew; four are global inputs to the PLD and one is a dedicated input providing the embedded processor stripe reference clock. The four PLD clocks service the ClockLock™ and ClockBoost™ circuitry on the Excalibur device. Table 30 lists all the clock sources on the development board. Table 30.
EPXA10 Development Board Hardware Reference Manual Table 30. EPXA10 Development Board Clock Sources (Part 2 of 2) EPXA10 Pin Name EPXA10 Pin Number Connection To Description Expansion Board Name Connector Connection CLKLK_FB1p AL28 CLK0_FBp Dedicated pin that allows external feedback to the PLL U125.197 CLK0_FBp CLKLK_FB2p K3 TP_CLK1_FBp Dedicated pin that allows external feedback to the PLL U125.
EPXA10 Development Board Hardware Reference Manual Sources for the Stripe Clock Reference There are three options for providing a source for the stripe clock reference: ■ ■ ■ External clock generator Main clock An alternative crystal oscillator Methods of selecting these options are given below.
EPXA10 Development Board Hardware Reference Manual Test & Debugging Features The development board includes the following test features: ■ ■ ■ JTAG connectors for use with either the MasterBlaster or ByteBlasterMV, or Multi-ICE Test connectors provided for debugging with a logic analyzer Matched impedance connectors (MICTORs), which can be used for debugging the individual interfaces JTAG Programming Chain There are two JTAG connectors on the EPXA10 development board. Each is connected to a JTAG chain.
EPXA10 Development Board Hardware Reference Manual Table 31. Bypass Settings for EPC2 JP57 Pins 1 & 2 Connected JP57 Pins 2 & 3 Connected JP50 Pins 1 & 2 Connected Bypass EPC2 (U7-U8) Bypass all EPC2s (U1-U8) JP50 Pins 2 & 3 Connected No bypass No bypass Jumper J14 with pins 1-2 connected is used to bypass PCI card 2 (U24) when only one PCI card is required—PCI card 1 (U23) must be used.
EPXA10 Development Board Hardware Reference Manual By setting JSELECT to 1, you can use Multi-ICE for downloading and debugging the software, and MasterBlaster/ByteBlasterMV for downloading and debugging the hardware. This is shown in Figure 12. Figure 12.
EPXA10 Development Board Hardware Reference Manual Figure 13.
EPXA10 Development Board Hardware Reference Manual Table 32. MICTOR Interface Device Reference (Part 2 of 2) Reference Part Number Manufacturer Website Address Description TRACE PORT AMP ref 2-767004-2 AMP www.amp.com ETM9 U13 AMP ref 2-767004-2 AMP www.amp.com UART and EBI Debugging The ETM9 trace module MICTOR connector is used in conjunction with trace tools such as ARM Trace and Lauterbach to debug the software in real time.
EPXA10 Development Board Hardware Reference Manual Figure 14 shows the UART DB9 male connector. Figure 14. DTE UART DB9 Male Connector 1 2 6 4 3 7 8 5 9 Table 34 lists the Ethernet RJ-45 male connector pin-outs. Figure 15 shows the Ethernet RJ-45 male connector. Table 34. Ethernet RJ-45 Male Connector Pin-Outs Pin Signal Description 1 TD+ Transmit data + 2 TD– Transmit data – 3 RD+ Read data + 4 N.C. No connection 5 N.C. No connection 6 RD– Read data – 7 N.C.
EPXA10 Development Board Hardware Reference Manual Table 35 lists the SDRAM DIMM socket pin-outs. Table 35. SDRAM DIMM Socket Pin-Outs (Part 1 of 2) Pin Signal 1 Vss Pin Signal 2 DQ0 Pin Signal 3 DQ1 Pin SIgnal 4 DQ2 5 DQ3 6 Vdd 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11 DQ8 12 Vss 16 DQ12 13 DQ9 14 DQ10 15 DQ11 17 DQ13 18 Vdd 19 DQ14 20 DQ15 21 N.C./CB0 22 N.C./CB1 23 Vss 24 N.C./CB8 25 N.C.
EPXA10 Development Board Hardware Reference Manual Table 35. SDRAM DIMM Socket Pin-Outs (Part 2 of 2) Pin Signal Pin Signal Pin Signal 143 Vdd Pin SIgnal 141 DQ50 142 DQ51 144 DQ52 145 /N.C.-NIRQ 146 VREF-N.C. 147 N.C. 148 Vss 149 DQ53 150 DQ54 151 DQ55 152 Vss 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 Vdd 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 Vss 163 CK3 164 N.C. 165 SA0 166 SA1 167 SA2 168 Vdd Table 36 lists the flash memory pin assignments. Table 36.
EPXA10 Development Board Hardware Reference Manual Table 37 lists the pin assignments on the PCI connectors. Table 37. PCI Card Connector Pin A1 Signal –12 V Pin A2 Signal TCK Pin B1 Signal TRST# Pin SIgnal B2 +12 V A3 GND A4 TDO B3 TMS B4 TDI A5 +5 V A6 +5 V B5 +5 V B6 INTA# B8 +5 V A7 INTB# A9 PRSNT1# A10 A8 RESERVED B9 RESERVED B10 V I/O A11 PRSNT2# A12 RESERVED B11 RESERVED B12 RESERVED A13 RESERVED A14 RESERVED B13 RESERVED B14 3.
EPXA10 Development Board Hardware Reference Manual Table 38 lists the pin assignments for the ETM9 trace port. Table 38. Trace Port Connections Pin Signal 1 N.C. Description No connection Pin Signal 2 N.C. Description No connection 3 N.C. No connection 4 N.C.
EPXA10 Development Board Hardware Reference Manual Tables 39 to 43 list the pin assignments for the devices connected to MICTOR interfaces. Table 39. MICTOR Connector: EBI Pin Signal 1 N.C. Description No connection Pin Signal 2 N.C. Description No connection 3 N.C. No connection 4 N.C.
EPXA10 Development Board Hardware Reference Manual Table 40. MICTOR Connector: SDRAM Part 1 Pin Signal 1 N.C. Description Signal Description No connection 2 N.C. No connection 3 N.C. No connection 4 N.C.
EPXA10 Development Board Hardware Reference Manual Table 41. MICTOR Connector: SDRAM Part 2 Pin Signal 1 N.C. Description No connection Pin Signal 2 N.C. Description No connection 3 N.C. No connection 4 N.C.
EPXA10 Development Board Hardware Reference Manual Table 42. MICTOR Connector: Configuration, EBI and UART Pin Signal 1 N.C. Pin Signal Description No connection 2 N.C. No connection 3 N.C. No connection 4 N.C.
EPXA10 Development Board Hardware Reference Manual Table 43. MICTOR Connector: JTAG, Clocks & I/O Pin Signal Description 1 N.C. Pin Signal Description Standard I/O (not used) 2 N.C. 3 N.C. 4 N.C.
EPXA10 Development Board Hardware Reference Manual Table 44 lists the pin assignments on the MasterBlaster/ByteBlasterMV connector. Table 44.
EPXA10 Development Board Hardware Reference Manual Table 45. Multi-ICE Connector (Part 2 of 2) Pin Signal 17 N.C. Development Board Pin-Outs & Signals Description No connection Direction N/A 18 GND Ground N/A 19 NA No connection N/A 20 GND Ground N/A The main component of the development board is the EPXA10F1020C2 device. The pins on the EPXA10 device are assigned to functions on the board.
EPXA10 Development Board Hardware Reference Manual Table 46.
EPXA10 Development Board Hardware Reference Manual SDR SDRAM Interface The SDRAM module is 64 bits wide, and the general-purpose memory data bus is 32 bits wide. To allow access to the entire SDRAM memory array, data bus pins are doubled. This means that the upper half of the data bus is connected to the lower half. For example, GPM_D(0) is connected to data pin 0 and data pin 32 on the SDRAM DIMM. Ensure that only 32 bits of the SDRAM data bus are enabled at a time (D[31..0] or D[63..
EPXA10 Development Board Hardware Reference Manual Table 48 lists the SDRAM data bank and address bus pin-outs. Table 48.
EPXA10 Development Board Hardware Reference Manual Table 49. EBI Control Signal Pin-Outs Signal Name EPXA10 Device Pin Description EBI_BE0 F27 Byte enable EBI_BE1 E27 Byte enable EBI_OE F26 Output enable EBI_WE E26 Write enable EBI_CS0 A25 Chip select EBI_CS1 B25 Chip select EBI_CS2 C25 Chip select EBI_CS3 D25 Chip select EBI_CLK E25 EBI clock EBI_ACK F25 EBI acknowledge Table 50 shows the EBI data bank and address bus pin-outs. Table 50.
EPXA10 Development Board Hardware Reference Manual UART1 and UART2 Table 51 details the pins used for UARTs 1 and 2. Table 51. Extension Header UARTs 1 & 2 I/O Pin-Outs PLD UART Embedded Stripe UART EPXA10 Device Pin Device Signal Expansion Board EPXA10 Device Pin Device Signal Expansion Board Connector Connector J27 UART1_DTR_N U126.171 G28 UART_CTS_N N.C. J29 UART1_TXD K29 U126.174 D29 UART_RXD N.C. UART1_RXD_N U126.177 E28 UART_RI_N K27 N.C. UART1_DSR_N U126.179 C28 UART_RTS_N N.C.
EPXA10 Development Board Hardware Reference Manual Fast I/O Pins Table 53 details the pins used for the EPXA10 fast I/O pins. Table 53. EPXA10 Fast I/O Pins EPXA10 Pin Name Description Pin Board Connector Board Name FAST0 Dedicated fast I/O pins E13 U126.133 FAST0 FAST1 Dedicated fast I/O pins E12 U126.134 FAST1 FAST2 Dedicated fast I/O pins AM18 U126.
EPXA10 Development Board Hardware Reference Manual Table 55.
EPXA10 Development Board Hardware Reference Manual Table 55. EPXA10 Development Board Test Points Test Point Connected To –12V –5V Test points for input power supply 1.8V 12V 2.5V 3.3V 5V U155 ATX POWER_OK TP1 I2C Test Points for DIMM Socket TP2 TP3 TP4 TP5 Expansion Header I/O Pins Table 56 lists the remaining I/O pins on the EPXA10 development board daughter cards, and their assignments on the EPXA10 device.
EPXA10 Development Board Hardware Reference Manual Table 56. Development Board Expansion Header I/O Pin-Outs (Part 2 of 5) EPXA10 Device Board Connector EPXA10 Device Board Connector EPXA10 Device Board Connector AC11 U124.1 AC12 U123.166 AC13 U123.147 AC14 U123.139 AC15 U123.126 AC16 U123.112 AC2 U126.48 AC23 U125.51 AC24 U125.40 AC25 U125.31 AC26 U124.144 AC27 U124.155 AC28 U124.143 AC29 U124.134 AC30 U126.83 AC31 U126.78 AC32 U126.77 AC4 U125.115 AC5 U125.
EPXA10 Development Board Hardware Reference Manual Table 56. Development Board Expansion Header I/O Pin-Outs (Part 3 of 5) EPXA10 Device Board Connector EPXA10 Device Board Connector EPXA10 Device Board Connector AH11 U123.164 AH12 U123.155 AH13 U123.146 AH14 U123.132 AH15 U123.119 AH16 U123.106 AH2 U126.57 AH23 U125.48 AH24 U125.39 AH25(1) U125.24 AH26 U125.15 AH27 U125.13 AH28 U125.9 AH29 U124.115 AH30 U124.118 AH31 U126.68 AH32 U126.69 AH4 U124.55 AH5 U124.
EPXA10 Development Board Hardware Reference Manual Table 56. Development Board Expansion Header I/O Pin-Outs (Part 4 of 5) EPXA10 Device Board Connector EPXA10 Device Board Connector EPXA10 Device Board Connector E31 U126.128 E32 U126.127 E4 U123.77 E5 U123.84 E6 U123.172 E7 U123.174 E8 U123.179 E9 U123.178 F5 U123.83 G5 U123.81 H1 U126.20 H2 U126.21 H30 U126.85 H31 U126.124 H32 U126.125 H4 U123.75 H5 U123.80 J1 U126.23 J2 U126.24 J26 U126.170 J27 U126.
EPXA10 Development Board Hardware Reference Manual Table 56. Development Board Expansion Header I/O Pin-Outs (Part 5 of 5) EPXA10 Device Board Connector EPXA10 Device Board Connector EPXA10 Device Board Connector R6 U123.23 R9 U123.44 T7 U123.17 R7 U123.29 R8 U123.33 T5 U123.13 T6 U123.11 T8 U123.24 T10 U123.39 T11 U123.41 T12 U123.45 T13 U123.47 T21 U124.174 T22 U124.179 T23 U124.81 T25 U124.69 T26 U124.65 T27 U124.57 T28 U124.64 T29 U124.63 T4 U123.36 U10 U123.
EPXA10 Development Board Hardware Reference Manual General Usage Guidelines To use the development board properly, and to avoid damage to it, follow the guidelines in this section. Anti-static Handling Before handling the card, you should take proper anti-static precautions, otherwise the board can be damaged.
EPXA10 Development Board Hardware Reference Manual Power Consumption Power consumption issues need to be addressed only if the board is powered from a terminal strip and not the provided ATX power supply adaptor. Altera recommends that you monitor the input current to ensure that sufficient power is supplied. The power required by the board is directly related to the following: ■ ■ ■ Number of interfaces used Density and speed of the device Population of the interfaces The typical maximum current is 5.
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