Specifications

ChangesVersionDate
• Added note to indicate that the figures shown are the top view of the
silicon die.
• Removed DPA support.
• Updated clock resources table.
• Updated diagrams for GCLK, RCLK, and PCLK networks.
• Updated diagram for clock sources per quadrant.
• Updated dual-regional clock region for Cyclone V SoC devices support.
• Restructured and updated tables for clock input pin connectivity to the
GCLK and RCLK networks.
• Added tables for clock input pin connectivity to the GCLK and RCLK
networks for Cyclone V SoC devices.
• Updated PCLK control block diagram.
• Updated information on clock power down.
• Added diagram for PLL physical counter orientation.
• Updated PLL locations diagrams.
• Updated fractional PLL high-level block diagram.
•
Removed information on pfdena PLL control signal.
• Removed information on PLL Compensation assignment in the
Quartus II software.
• Updated the fractional value for PLL in fractional mode.
• Reorganized content and updated template.
2012.12.28December 2012
• Restructured chapter.
• Updated Figure 4–4, Figure 4–6, Figure 4–7, Figure 4–11, Figure 4–13,
Figure 4–15, Figure 4–16, Figure 4–17, Figure 4–19, and Figure 4–20.
• Updated Table 4–2, Table 4–3, and Table 4–5.
• Added “Clock Regions”, “Clock Network Sources”, “Clock Output
Connections”, “Clock Enable Signals”, “PLL Control Signals”, “Clock
Multiplication and Division”, “Programmable Duty Cycle”, “Clock
Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift”
sections.
2.0June 2012
Updated Table 4–2.1.1February 2012
Initial release.1.0October 2011
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52004
Document Revision History
4-34
2013.05.06