Specifications

Figure 4-32: VCO Switchover Operating Frequency
∆F
vco
Primary Clock Stops Running
VCO Tracks Secondary Clock
Switchover Occurs
PLL Reconfiguration and Dynamic Phase Shift
For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661.
Related Information
AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and
ALTERA_PLL_RECONFIG Megafunctions
Document Revision History
ChangesVersionDate
• Added link to the known document issues in the Knowledge Base.
• Updated PCLK clock sources in hierarchical clock networks in each
spine clock per quadrant diagram.
• Added PCLK networks in clock network sources section.
• Updated dedicated clock input pins in clock network sources section.
• Added descriptions for PLLs located in a strip.
• Added information on PLL physical counters.
• Updated the fractional PLL architecture diagram to add dedicated
refclk input port and connections.
• Updated PLL support for EFB mode.
• Updated the scaling factors for PLL output ports.
• Updated the fractional value for PLL in fractional mode.
• Moved all links to the Related Information section of respective topics
for easy reference.
• Reorganized content.
2013.05.06May 2013
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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4-33
PLL Reconfiguration and Dynamic Phase Shift
CV-52004
2013.05.06