Specifications

Figure 4-30: Clock Switchover Using the clkswitch (Manual) Control
This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, both
clock sources are functional and inclk0 is selected as the reference clock; the clkswitch signal goes
high, which starts the switchover sequence. On the falling edge of inclk0, the counters reference clock,
muxout, is gated off to prevent clock glitching. On the falling edge of inclk1, the reference clock multiplexer
switches from inclk0 to inclk1 as the PLL reference. The activeclock signal changes to indicate
the clock which is currently feeding the PLL.
inclk0
inclk1
muxout
clkbad0
clkbad1
activeclock
clkswitch
To initiate a manual clock switchover event,
both inclk0 and inclk1 must be running when
the clkswitch signal goes high.
In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch
signal. Since both clocks are still functional during the manual switch, neither clkbad signal goes high.
Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not
cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again,
the process repeats.
The clkswitch signal and automatic switch work only if the clock being switched to is available. If the
clock is not available, the state machine waits until the clock is available.
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Manual Clock Switchover
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected
as the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high,
and being held high for at least three inclk cycles.
You must bring the clkswitch signal back low again to perform another switchover event. If you do not
require another switchover event, you can leave the clkswitch signal in a logic high state after the initial
switch.
Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the clkswitchsignal minimum
high time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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4-31
Manual Clock Switchover
CV-52004
2013.05.06