Specifications

period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL
may lose lock after the switchover is completed and needs time to relock.
Altera recommends resetting the PLL using the areset signal to maintain the phase relationships
between the PLL input and output clocks when using clock switchover.
Note:
Figure 4-29: Automatic Switchover After Loss of Clock Detection
This figure shows an example waveform of the switchover feature in automatic switchover mode. In this
example, the inclk0 signal is stuck low. After the inclk0 signal is stuck at low for approximately two
clock cycles, the clock sense circuitry drives the clkbad[0] signal high. Since the reference clock signal
is not toggling, the switchover state machine controls the multiplexer through the clkswitch signal to
switch to the backup clock, inclk1.
inclk0
inclk1
muxout
clkbad0
clkbad1
activeclock
Switchover is enabled on the falling
edge of inclk0 or inclk1, depending
on which clock is available. In this
figure, switchover is enabled on the
falling edge of inclk1.
Automatic Switchover with Manual Override
In automatic switchover with manual override mode, you can use the clkswitch signal for user- or system-
controlled switch conditions. You can use this mode for same-frequency switchover, or to switch between
inputs of different frequencies.
For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the
clkswitch signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1)
frequencies with a frequency difference of more than 100% (2×).
This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a
system-controlled switchover between the frequencies of operation.
You must choose the backup clock frequency and set the M, N, C, and K counters so that the VCO operates
within the recommended operating frequency range. The ALTERA_PLL MegaWizard Plug-in Manager
notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
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CV-52004
Automatic Switchover with Manual Override
4-30
2013.05.06