Specifications

Figure 4-28: Automatic Clock Switchover Circuit Block Diagram
This figure shows a block diagram of the automatic switchover circuit built into the PLL.
Clock
Sense
Switchover
State Machine
Clock Switch
Control Logic
N Counter
inclk0
inclk1
Multiplexer
Out
clkbad[0]
clkbad[1]
activeclock
clkswitch
refclk
fbclk
clksw
PFD
When the current reference clock is not present, the clock sense block automatically switches to the backup
clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1
port of the PLL in your design.
The clock switchover circuit sends out three status signals—clkbad[0], clkbad[1], and
activeclock—from the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two
clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has
stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1
is greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected
as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than
20%, the activeclock signal is the only valid status signal.
Glitches in the input clock may cause the frequency difference between the input clocks to be more
than 20%.
Note:
Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current
reference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1
any number of times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock,
the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In this
case, inclk1 becomes the reference clock for the PLL.
When using automatic clock switchover mode, the following requirements must be satisfied:
• Both clock inputs must be running.
• The period of the two clock inputs can differ by no more than 20%.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated
and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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4-29
Automatic Switchover
CV-52004
2013.05.06