Specifications

Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature
is supported on the PLL post-scale counters.
The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To
determine the duty cycle choices, the Quartus II software uses the frequency input and the required multiply
or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50%
divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the counter
driving the fbin pin to 50%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise
non-overlapping clocks.
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature
for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock
if the previous clock stops running. The design can perform clock switchover automatically when the clock
is no longer toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Cyclone V PLLs:
• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current
reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
•
Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When the
clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the
reference clock to the PLL is switched from inclk0 to inclk1, or vice-versa.
• Automatic switchover with manual override—This mode combines automatic switchover and manual
clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover
function. As long as the clkswitch signal is high, further switchover action is blocked.
Automatic Switchover
Cyclone V PLLs support a fully configurable clock switchover capability.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52004
Programmable Duty Cycle
4-28
2013.05.06