Specifications
Related Information
PLL External Clock I/O Pins on page 4-19
Provides more information about PLL clock outputs.
Clock Multiplication and Division
Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The
input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control
loop drives the VCO to match f
in
× (M/N).
The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency,
multiplication, and division values entered into the ALTERA_PLL megafunction.
Post-Scale Counter, K
A post-scale counter, K, is inserted after the VCO. When you enable the VCO post-scale counter, the counter
divides the VCO frequency by two. When the K counter is bypassed, the VCO frequency goes to the output
port without being divided by two.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C, that divides down the output from the K counter. For
multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output
frequencies that meets its frequency specifications. For example, if the output frequencies required from
one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common multiple
of 33 and 66 MHz within the VCO range). Then the post-scale counters, C, scale down the VCO frequency
for each output port.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M, with a range of 1 to 512 for both M and
N. The N counter does not use duty-cycle control because the only purpose of this counter is to calculate
frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values
for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects
the divide value for a given counter.
Delta-Sigma Modulator
The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the PLL to operate
in fractional mode. The DSM dynamically changes the M counter divide value on a cycle to cycle basis. The
different M counter values allow the "average" M counter value to be a non-integer.
Fractional Mode
In fractional mode, the M counter divide value equals to the sum of the "clock high" count, "clock low" count,
and the fractional value. The fractional value is equal to K/2^X, where K is an integer between 0 and (2^X – 1),
and X = 8, 16, 24, or 32.
Integer Mode
For PLL operating in integer mode, M is an integer value and DSM is disabled.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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Clock Multiplication and Division
CV-52004
2013.05.06