Specifications

Figure 4-24: ZDB Mode in Cyclone V PLLs
inclk
÷N PFD
VCO
CP/LF
C0
C1
C2
C3
C4
C5
C6
C7
C8
M
EXTCLKOUT[1]
EXTCLKOUT[0]
fbout
fbin
210
FPLL_<#>_FB
Multiplexer
Figure 4-25: Example of Phase Relationship Between the PLL Clocks in ZDB Mode
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
Phase Aligned
PLL Reference
Clock at the Input Pin
The internal PLL clock
output can lead or lag
the external PLL clock
outputs.
Related Information
PLL External Clock I/O Pins on page 4-19
Provides more information about PLL clock outputs.
External Feedback Mode
In EFB mode, the output of the M counter (fbout) feeds back to the PLL fbin input (using a trace on the
board) and becomes part of the feedback loop.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
4-25
External Feedback Mode
CV-52004
2013.05.06