Specifications

Figure 4-23: Example of Phase Relationship Between the PLL Clocks in Normal Mode

PLL Clock at the

Dedicated PLL

Clock Outputs

Phase Aligned

PLL Reference

Clock at the Input Pin

The external clock output

can lead or lag the PLL

internal clock signals.

Zero-Delay Buffer Mode

In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through

the device. This mode is supported on all Cyclone V PLLs.

When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee

clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock

input or output pins.

To ensure phase alignment between the clk pin and the external clock output (CLKOUT) pin in ZDB mode,

instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path

connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a

single-ended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output

delay from the clock output port of the PLL to the external clock output pin.

To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O

pin.

Note:

Clock Networks and PLLs in Cyclone V Devices

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Zero-Delay Buffer Mode

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2013.05.06