Specifications

Figure 4-21: Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode
Data Pin
Data at the Register
Clock at the Register
PLL Reference Clock
at the Input Pin
Direct Compensation Mode
In direct compensation mode, the PLL does not compensate for any clock networks. This mode provides
better jitter performance because the clock feedback into the PFD passes through less circuitry. Both the
PLL internal- and external-clock outputs are phase-shifted with respect to the PLL clock input.
Figure 4-22: Example of Phase Relationship Between the PLL Clocks in Direct Compensation Mode
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL
Clock Outputs
Phase Aligned
The PLL clock outputs
lag the PLL input clocks
depending on routing
delays.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external clock output pin has
a phase delay relative to the clock input pin if connected in this mode. The Quartus II TimeQuest Timing
Analyzer reports any phase difference between the two. In normal mode, the delay introduced by the GCLK
or RCLK network is fully compensated.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
4-23
Direct Compensation Mode
CV-52004
2013.05.06