Specifications

Fractional PLL Usage
You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode.
One fractional PLL can use up to 9 output counters and all external clock outputs.
Fractional PLLs can be used as follows:
• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference
clock source
• Compensate clock network delay
• Zero delay buffering
• Transmit clocking for transceivers
PLL External Clock I/O Pins
All Cyclone V external clock outputs for corner fractional PLLs (that are not from the PLL strips) are dual-
purpose clock I/O pins. Two external clock output pins associated with each corner fractional PLL are
organized as one of the following combinations:
• Two single-ended clock outputs
• One differential clock output
• Two single-ended clock outputs and one single-ended clock input in the I/O driver feedback for zero
delay buffer (ZDB) mode support
• One single-ended clock output and one single-ended feedback input for single-ended external feedback
(EFB) mode support
• One differential clock output and one differential feedback input for differential EFB support
The middle fractional PLLs on the left side of Cyclone V E A7 device, Cyclone V GX C7 device, and
Cyclone V GT D7 device do not support external clock outputs.
Note:
The following figure shows that any of the output counters (C[0..8]) or the M counter on the PLLs can
feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins
available from a given PLL.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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Fractional PLL Usage
CV-52004
2013.05.06