Specifications

Figure 4-17: PLL Locations for Cyclone V E A9 Device, Cyclone V GX C9 Device, and Cyclone V GT D9 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Pins
CLK[4..5][p,n]
4
Pins
Logical Clocks
2
Logical
Clocks
2
Logical Clocks
Pins
CLK[8..11][p,n]
CLK[0..3][p,n]
CLK[2,3]
CLK[10,11]
2
4
Logical
Clocks
4
Logical Clocks
FRACTIONALPLL_X0_Y81
FRACTIONALPLL_X0_Y64
FRACTIONALPLL_X0_Y39
FRACTIONALPLL_X0_Y22
FRACTIONALPLL_X0_Y1
FRACTIONALPLL_X121_Y1
4
4
4
4
PLL Strip
4
4
Pins
CLK[6..7][p,n]
FRACTIONALPLL_X0_Y108
FRACTIONALPLL_X121_Y108
2
Logical
Clocks
4
Fractional PLL Architecture
Figure 4-18: Fractional PLL High-Level Block Diagram for Cyclone V Devices
Clock
Switchover
Block
inclk0
inclk1
Dedicated
Clock Inputs
Cascade Input
from Adjacent PLL
pfdena
clkswitch
clkbad0
clkbad1
activeclock
PFD
Lock
Circuit
locked
÷N
CP LF
VCO
÷2
GCLK/RCLK
8
4
FBIN
DIFFIOCLK Network
GCLK/RCLK Network
Direct Compensation Mode
ZDB, External Feedback Modes
LVDS Compensation Mode
Source Synchronous, Normal Modes
÷C0
÷C1
÷C2
÷C3
÷C8
÷M
PLL Output Multiplexer
Casade Output
to Adjacent PLL
GCLKs
RCLKs
External Clock Outputs
TX Serial Clock
TX Load Enable
FBOUT
External Memory
Interface DLL
8
PMA Clocks
Delta Sigma
Modulator
Dedicated refclk
VCO Post-Scale
Counter K
Only C0 and C2 drive the TX
serial clock and C1 and C3
can drive the TX load enable.
This FBOUT port is fed by
the M counter in the PLLs.
For single-ended clock inputs, only the CLK<#>p pin
has a dedicated connection to the PLL. If you use the
CLK<#>n pin, a global or regional clock is used.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
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CV-52004
Fractional PLL Architecture
4-18
2013.05.06