Specifications

Figure 4-16: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, Cyclone V GT D7 Device,
Cyclone V SE A5 and A6 Devices, Cyclone V SX C5 and C6 Devices, and Cyclone V ST D5 and D6 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
2
4
4
Pins
Logical Clocks
2
Logical
Clocks
2
Logical Clocks
Pins
4
Logical Clocks
CLK[8..11][p,n]
CLK[0..3][p,n]
Pins
Pins
Logical
Clocks
24
CLK[4..5][p,n]
CLK[6..7][p,n]
FRACTIONALPLL_X0_Y56
FRACTIONALPLL_X0_Y32
FRACTIONALPLL_X0_Y74
FRACTIONALPLL_X0_Y15
FRACTIONALPLL_X89_Y74 (1)
FRACTIONALPLL_X89_Y1
2
4
4
4
FRACTIONALPLL_X0_Y1
CLK[2,3]
CLK[10,11]
PLL Strip
FRACTIONALPLL_X89_Y74 is not
available for Cyclone V SE A5 and A6
devices, Cyclone V SX C5 and C6
devices, and Cyclone V ST D5
and D6 devices.
Logical
Clocks
2
4
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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4-17
PLL Locations in Cyclone V Devices
CV-52004
2013.05.06