Specifications

Cyclone V PLLs
PLLs provide robust clock management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
The Cyclone V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs.
The output counters in Cyclone V devices are dedicated to each fractional PLL that support integer or
fractional frequency synthesis.
The Cyclone V devices offer up to 8 fractional PLLs in the larger densities.
Table 4-7: PLL Features in Cyclone V Devices —Preliminary
SupportFeature
YesInteger PLL
YesFractional PLL
9
C output counters
1 to 512
M, N, C counter sizes
2 single-ended and 1 differentialDedicated external clock outputs
4 single-ended or 4 differentialDedicated clock input pins
Single-ended or differentialExternal feedback input pin
Yes
(4)
Spread-spectrum input clock tracking
YesSource synchronous compensation
YesDirect compensation
YesNormal compensation
YesZero-delay buffer compensation
YesExternal feedback compensation
YesLVDS compensation
78.125 ps
(5)
Phase shift resolution
YesProgrammable duty cycle
YesPower down mode
(4)
Provided input clock jitter is within input jitter tolerance specifications. The modulation frequency of the input
clock is below the PLL bandwidth which is specified in the Fitter report.
(5)
The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
degree increments, the Cyclone V device can shift all output frequencies in increments of at least 45°. Smaller
degree increments are possible depending on the frequency and divide parameters.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52004
Cyclone V PLLs
4-14
2013.05.06