Specifications

Figure 4-7: RCLK Control Block for Cyclone V Devices
CLKp
Pin
PLL Counter
Outputs
Internal Logic
CLKn
Pin
Enable/
Disable
RCLK
Internal
Logic
Static Clock Select
2
When the device is in user mode,
you can only set the clock select
signals through a configuration file
(.sof or .pof); they cannot be
controlled dynamically.
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the RCLK.
You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the
inputs using the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1]
ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.
Note:
Related Information
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Provides more information about ALTCLKCTRL megafunction.
PCLK Control Block
To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .
Figure 4-8: Horizontal PCLK Control Block for Cyclone V Devices
HSSI Output
Internal Logic
Static Clock Select
Horizontal PCLK
External PLL Clock Output Control Block
You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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4-11
PCLK Control Block
CV-52004
2013.05.06