Specifications

Pin Mapping in Cyclone V Devices
Table 4-6: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs
Fed byClock
Any of the four dedicated clock pins on the same side of the Cyclone V
device.
inclk[0] and inclk[1]
•
PLL counters C0 and C2 from PLLs on the same side of the clock control
block (for top, bottom, and right side of the Cyclone V device).
•
PLL counter C4 from PLLs on the same side of the clock control block
(for left side of the Cyclone V device).
inclk[2]
PLL counters C1 and C3 from PLLs on the same side of the clock control
block (for top, bottom, and right side of the Cyclone V device). This input
clock port is not connected for the clock control block on left side of the
Cyclone V device.
inclk[3]
GCLK Control Block
You can select the clock source for the GCLK select block either statically or dynamically using internal logic
to drive the multiplexer-select inputs.
When selecting the clock source dynamically, you can select up to two PLL counter outputs and up to two
clock pins.
Figure 4-6: GCLK Control Block for Cyclone V Devices
CLKp
Pins
PLL Counter
Outputs
CLKSELECT[1..0]
2
2
2
GCLK
Enable/
Disable
This multiplexer
supports user-controllable
dynamic switching
Internal
Logic
Internal
Logic
Static Clock
Select
PLL Counter
Outputs
CLKn
Pin
When the device is in user mode,
you can dynamically control the
clock select signals through
internal logic.
When the device is in user mode, you can
only set the clock select signals through a
configuration file (SRAM object file [.sof] or
programmer object file [.pof]) because the
signals cannot be controlled dynamically.
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the GCLK.
RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit
settings in the configuration file (.sof or .pof) generated by the Quartus II software.
Clock Networks and PLLs in Cyclone V Devices
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Pin Mapping in Cyclone V Devices
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2013.05.06