Specifications

Figure 4-5: Dual-Regional Clock Region for Cyclone V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Clock pins or PLL outputs can
drive half of the device to create
dual-regional clocking regions
for improved interface timing.
Clock Network Sources
In Cyclone V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, and internal
logic can drive the GCLK, RCLK, and PCLK networks.
Dedicated Clock Input Pins
You can use the dedicated clock input pins (CLK[0..11][p,n]) for high fan-out control signals, such
as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
CLK pins can be either differential clocks or single-ended clocks. When you use the CLK pins as single-ended
clock inputs, only the CLK<#>p pins have dedicated connections to the PLL. The CLK<#>n pins drive the
PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs.
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not
be able to fully compensate for the global or regional clock. Altera recommends using the CLK<#>p pins
for optimal performance when you use single-ended clock inputs to drive the PLLs.
Internal Logic
You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing and row clock to enable
internal logic to drive a high fan-out, low-skew signal.
Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Cyclone V PLLs. The input clock
to the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.
Note:
HSSI Outputs
Every three HSSI outputs generate a group of four PCLKs to the core.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
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Clock Network Sources
CV-52004
2013.05.06