Specifications

Figure 4-1: GCLK Networks in Cyclone V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
GCLK[12..15]
GCLK[8..11]
GCLK[4..7]
GCLK[0..3]
Q1
Q4
Q2
Q3
CLK[0..3][p,n]
CLK[8..11][p,n]
CLK[4..7][p,n]
For Cyclone V E A2 and
A4 devices, only
CLK[6][p,n] pins are
available.
GCLK network is not available in
quadrant 2 for Cyclone V GX C6
device, Cyclone V SE A5 and A6
devices, and Cyclone V ST D5 and
D6 devices.
Regional Clock Networks
RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock
insertion delay and skew for logic contained within a single device quadrant. The Cyclone V IOEs and
internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks
and other high fan-out control signals.
Figure 4-2: RCLK Networks in Cyclone V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
RCLK[64..69]
RCLK[70..75]
RCLK[82..87] RCLK[76..81]
RCLK[58..63]
RCLK[52..57]
RCLK[40..45]
RCLK[46..51]
RCLK[0..9] RCLK[10..19]
RCLK[30..39] RCLK[20..29]
CLK[8..11][p,n]
CLK[0..3][p,n]
CLK[4..7][p,n]
For Cyclone V E A2
and A4 devices, only
CLK[6][p,n] pins are
available.
Q1 Q2
Q3Q4
GCLK network is not
available in quadrant 2 for
Cyclone V GX C6 device,
Cyclone V SE A5 and A6
devices, and Cyclone V ST
D5 and D6 devices.
Clock Networks and PLLs in Cyclone V Devices
Altera Corporation
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CV-52004
Regional Clock Networks
4-4
2013.05.06