Specifications

Transmitter Blocks.........................................................................................................................5-62
Serializer Bypass for DDR and SDR Operations.......................................................................5-63
Differential Receiver in Cyclone V Devices...........................................................................................5-64
Receiver Blocks in Cyclone V Devices........................................................................................5-64
Receiver Mode in Cyclone V Devices.........................................................................................5-66
Receiver Clocking for Cyclone V Devices..................................................................................5-67
Differential I/O Termination for Cyclone V Devices...............................................................5-67
Source-Synchronous Timing Budget......................................................................................................5-68
Differential Data Orientation.......................................................................................................5-68
Differential I/O Bit Position.........................................................................................................5-69
Transmitter Channel-to-Channel Skew.....................................................................................5-70
Receiver Skew Margin for LVDS Mode......................................................................................5-70
Document Revision History.....................................................................................................................5-72
External Memory Interfaces in Cyclone V Devices............................................6-1
External Memory Performance..................................................................................................................6-2
HPS External Memory Performance.........................................................................................................6-2
Memory Interface Pin Support in Cyclone V Devices............................................................................6-2
Guideline: Using DQ/DQS Pins....................................................................................................6-3
DQ/DQS Bus Mode Pins for Cyclone V Devices........................................................................6-3
DQ/DQS Groups in Cyclone V E..................................................................................................6-4
DQ/DQS Groups in Cyclone V GX...............................................................................................6-6
DQ/DQS Groups in Cyclone V GT...............................................................................................6-9
DQ/DQS Groups in Cyclone V SX..............................................................................................6-11
DQ/DQS Groups in Cyclone V ST..............................................................................................6-11
External Memory Interface Features in Cyclone V Devices................................................................6-11
UniPHY IP......................................................................................................................................6-12
External Memory Interface Datapath.........................................................................................6-12
DQS Phase-Shift Circuitry............................................................................................................6-13
PHY Clock (PHYCLK) Networks...............................................................................................6-20
DQS Logic Block............................................................................................................................6-22
Dynamic OCT Control.................................................................................................................6-24
IOE Registers..................................................................................................................................6-25
Delay Chains...................................................................................................................................6-27
I/O and DQS Configuration Blocks............................................................................................6-28
Hard Memory Controller.........................................................................................................................6-29
Features of the Hard Memory Controller..................................................................................6-29
Multi-Port Front End....................................................................................................................6-31
Altera Corporation
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
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