Specifications

Source of Clock Resource
Number of Resources
Available
DeviceClock Resource
—Cyclone V E A2 and A4
PCLK networks
PLD-transceiver interface clocks,
I/O pins, and logic array
6Cyclone V GX C3
12
• Cyclone V E A5
• Cyclone V GX C4and
C5
• Cyclone V GT D5
18
• Cyclone V E A7
• Cyclone V GX C7
• Cyclone V GT D7
• Cyclone V SE A5 and
A6
• Cyclone V SX C5 and
C6
• Cyclone V ST D5 and
D6
24
• Cyclone V E A9
• Cyclone V GX C9
• Cyclone V GT D9
16 GCLKs + 22 RCLKs38All
GCLKs and RCLKs
per quadrant
16 GCLKs + 88 RCLKs104All
GCLKs and RCLKs
per device
For more information about the clock input pins connections, refer to the pin connection guidelines.
Related Information
Cyclone V Device Family Pin Connection Guidelines
Types of Clock Networks
Global Clock Networks
Cyclone V devices provide GCLKs that can drive throughout the device. The GCLKs serve as low-skew clock
sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP),
embedded memory, and PLLs. Cyclone V I/O elements (IOEs) and internal logic can also drive GCLKs to
create internally-generated global clocks and other high fan-out control signals, such as synchronous or
asynchronous clear and clock enable signals.
Altera Corporation
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
4-3
Types of Clock Networks
CV-52004
2013.05.06