Specifications

Table 4-1: Clock Resources in Cyclone V Devices—Preliminary
Source of Clock Resource
Number of Resources
Available
DeviceClock Resource
CLK[0..11][p,n] pins
24 single-ended or 12
differential
• Cyclone V E A5, A7,
and A9
• Cyclone V GX C4,
C5, C7, and C9
• Cyclone V GT D5,
D7, and D9
Clock input pins
CLK[0..3][p,n],
CLK[6][p,n],
CLK[8..11][p,n] pins
18 single-ended or 9
differential
• Cyclone V E A2 and
A4
• Cyclone V GX C3
CLK[0..7][p,n] pins
16 single-ended or 8
differential
• Cyclone V SE A5 and
A6
• Cyclone V SX C5 and
C6
• Cyclone V ST D5 and
D6
CLK[0..11][p,n] pins, PLL
clock outputs, and logic array
• GCLK networks: 16
• RCLK networks: 88
• Cyclone V E A5, A7,
and A9
• Cyclone V GX C4,
C5, C7, and C9
• Cyclone V GT D5,
D7, and D9
GCLK and RCLK
networks
CLK[0..3][p,n],
CLK[6][p,n],
CLK[8..11][p,n] pins, PLL
clock outputs, and logic array
• Cyclone V E A2 and
A4
• Cyclone V GX C3
CLK[0..7][p,n] pins, PLL
clock outputs, and logic array
• GCLK networks: 16
• RCLK networks: 66
• Cyclone V SE A5 and
A6
• Cyclone V SX C5 and
C6
• Cyclone V ST D5 and
D6
Clock Networks and PLLs in Cyclone V Devices
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CV-52004
Clock Resources in Cyclone V Devices
4-2
2013.05.06