Specifications

Figure 3-15: 18-Bit Systolic FIR Mode for Cyclone V Devices
Input Register Bank
dataa_y0[17..0]
dataa_z0[17..0]
dataa_x0[17..0]
COEFSELA[2..0]
datab_y1[17..0]
datab_z1[17..0]
datab_x1[17..0]
COEFSELB[2..0]
+/-
Pre-Adder
+/-
Pre-Adder
+/-
Internal
Coefficient
Internal
Coefficient
Multiplier
Multiplier
Adder
+/-
Systolic
Registers (1)
Systolic
Register (1)
Chainout adder or
accumulator
+
Output Register Bank
chainin[43..0]
chainout[43..0]
Result[43..0]
18-bit Systolic FIR
x
x
Note:
1. The systolic registers have the same clock source as the output register bank.
18
18
18
18
18
18
3
3
44
44
44
27-Bit Systolic FIR Mode
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing
10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of 1,024 multiplier products.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.
Altera Corporation
Variable Precision DSP Blocks in Cyclone V Devices
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3-17
27-Bit Systolic FIR Mode
CV-52003
2013.05.06