Specifications

Block Architecture
The Cyclone V variable precision DSP block consists of the following elements:
• Input register bank
• Pre-adder
• Internal coefficient
• Multipliers
• Adder
• Accumulator and chainout adder
• Systolic registers
• Double accumulation register
• Output register bank
If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.
Figure 3-1: Variable Precision DSP Block Architecture for Cyclone V Devices
Input Register Bank
scanin
scanout
LOADCONST
ACCUMULATE
NEGATE
dataa_y0[18..0]
dataa_z0[17..0]
dataa_x0[17..0]
COEFSELA[2..0]
datab_y1[18..0]
datab_z1[17..0]
datab_x1[17..0]
COEFSELB[2..0]
SUB_COMPLEX
+/-
Pre-Adder
+/-
Pre-Adder
+/-
Internal
Coefficient
Internal
Coefficient
Multiplier
Adder
+/-
+/-
Systolic
Registers
(1)
Systolic
Register (1)
Chainout adder/
accumulator
+
Output Register Bank
Constant
Double
Accumulation
Register
chainin[63..0]
chainout[63..0]
Result[73..0]
Multiplier
x
x
CLK[2..0]
ENA[2..0]
ACLR[1..0]
Note:
1. When enabled, systolic registers are clocked with the same clock source as the output register bank.
Altera Corporation
Variable Precision DSP Blocks in Cyclone V Devices
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3-5
Block Architecture
CV-52003
2013.05.06