Specifications

Types of Clock Networks................................................................................................................4-3
Clock Sources Per Quadrant..........................................................................................................4-5
Types of Clock Regions...................................................................................................................4-6
Clock Network Sources...................................................................................................................4-7
Clock Output Connections.............................................................................................................4-9
Clock Control Block........................................................................................................................4-9
Clock Power Down........................................................................................................................4-12
Clock Enable Signals......................................................................................................................4-12
Cyclone V PLLs..........................................................................................................................................4-14
PLL Physical Counters in Cyclone V Devices............................................................................4-15
PLL Locations in Cyclone V Devices..........................................................................................4-15
Fractional PLL Architecture.........................................................................................................4-18
PLL External Clock I/O Pins........................................................................................................4-19
PLL Control Signals.......................................................................................................................4-20
Clock Feedback Modes..................................................................................................................4-21
Clock Multiplication and Division..............................................................................................4-27
Programmable Duty Cycle...........................................................................................................4-28
Clock Switchover...........................................................................................................................4-28
PLL Reconfiguration and Dynamic Phase Shift........................................................................4-33
Document Revision History.....................................................................................................................4-33
I/O Features in Cyclone V Devices......................................................................5-1
I/O Resources Per Package for Cyclone V Devices.................................................................................5-1
I/O Vertical Migration for Cyclone V Devices........................................................................................5-4
Verifying Pin Migration Compatibility........................................................................................5-5
I/O Standards Support in Cyclone V Devices..........................................................................................5-5
I/O Standards Support for FPGA I/O in Cyclone V Devices....................................................5-5
I/O Standards Support for HPS I/O in Cyclone V Devices........................................................5-7
I/O Standards Voltage Levels in Cyclone V Devices...................................................................5-8
MultiVolt I/O Interface in Cyclone V Devices..........................................................................5-10
I/O Design Guidelines for Cyclone V Devices.......................................................................................5-11
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards...........................5-11
PLLs and Clocking.........................................................................................................................5-12
LVDS Interface with External PLL Mode...................................................................................5-15
Guideline: Use the Same V
CCPD
for All I/O Banks in a Group...............................................5-17
Guideline: Ensure Compatible V
CCIO
and V
CCPD
Voltage in the Same Bank......................5-18
Guideline: VREF Pin Restrictions...............................................................................................5-18
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......................5-18
Altera Corporation
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
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