Specifications

Figure 2-9: Address Clock Enable During the Write Cycle Waveform

This figure shows the address clock enable waveform during the write cycle.

inclock

wren

wraddress

a0 a1 a2 a3 a4 a5

an a0

a4 a5

latched address

(inside memory)

addressstall

data

01 02

03 04

contents at a0

contents at a1

contents at a2

contents at a3

contents at a4

contents at a5

Document Revision History

ChangesVersionDate

• Moved all links to the Related Information section of respective topics

for easy reference.

• Added link to the known document issues in the Knowledge Base.

• Updated the maximum operating frequency of the MLAB.

• Corrected the description about the "don't care" output mode for RAM

in mixed-port read-during-write.

• Reorganized the structure of the supported memory configurations

topics (single-port and mixed-width dual-port) to improve clarity about

maximum data widths supported for each configuration.

• Added a description to the table listing the maximum embedded memory

configurations to clarify that the information applies only to the single

port or ROM mode.

• Removed the topic about mixed-width configurations for MLABs and

added a note to clarify that MLABs do not support mixed-width

configuration.

2013.05.06May 2013

Embedded Memory Blocks in Cyclone V Devices

Altera Corporation

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CV-52002

Document Revision History

2-16

2013.05.06