Specifications

Memory Blocks Packed Mode Support
The M10K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The
Quartus II software automatically implements packed mode where appropriate by placing the physical RAM
block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM
blocks. The size of each independent single-port RAM must not exceed half of the target block size.
Memory Blocks Address Clock Enable Support
The embedded memory blocks support address clock enable, which holds the previous address value for as
long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-
port mode, each port has its own independent address clock enable. The default value for the address clock
enable signal is low (disabled).
Figure 2-7: Address Clock Enable
This figure shows an address clock enable block diagram. The address clock enable is referred to by the port
name addressstall.
address[0]
address[N]
addressstall
clock
1
0
address[0]
register
address[N]
register
address[N]
address[0]
1
0
Figure 2-8: Address Clock Enable During Read Cycle Waveform
This figure shows the address clock enable waveform during the read cycle.
inclock
rden
rdaddress
q (synch)
a0 a1 a2 a3 a4 a5
a6
q (asynch)
an a0
a4
a5
latched address
(inside memory)
dout0
dout1
dout4
dout4
dout5
addressstall
a1
doutn-1 doutn
doutn
dout0
dout1
Altera Corporation
Embedded Memory Blocks in Cyclone V Devices
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Memory Blocks Packed Mode Support
CV-52002
2013.05.06