Specifications

Data Bits Writtenbyteena[1:0]
[9:0]
—01
Table 2-13: byteena Controls in x40 Data Width
Data Bits Writtenbyteena[3:0]
[9:0][19:10][29:20][39:30]
1111 (default)
———
[39:30]
1000
——
[29:20]
—0100
—
[19:10]
——0010
[9:0]
———0001
Data Byte Output
In M10K blocks, the corresponding masked data byte output appears as a “don’t care” value.
In MLABs, when you de-assert a byte-enable bit during a write cycle, the corresponding data byte output
appears as either a “don't care” value or the current data at that location. You can control the output value
for the masked byte in the MLABs by using the Quartus II software.
RAM Blocks Operations
Figure 2-6: Byte Enable Functional Waveform
This figure shows how the wren and byteena signals control the operations of the RAM blocks. For the
M10K blocks, the write-masked data byte output appears as a “don’t care” value because the “current data”
value is not supported.
inclock
wren
address
data
byteena
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
don’t care: q (asynch)
current data: q (asynch)
an a0 a1 a2 a3 a4 a0
XXXXXXXX XXXXXXXX
ABCDEF12
ABCDEF12
XXXX XXXX1000 0100 0010 0001 1111
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFF12
FFFFFF12
FFFFEFFF
FFFFEFFF
FFCDFFFF
FFCDFFFF
ABFFFFFF
ABFFFFFF
ABFFFFFFdoutn
doutn
ABXXXXXX XXCDXXXX XXXXEFXX XXXXXX12 ABCDEF12
ABFFFFFFABCDEF12
Embedded Memory Blocks in Cyclone V Devices
Altera Corporation
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CV-52002
Data Byte Output
2-14
2013.05.06