Specifications

Independent Clock Enables in Clocking Modes
Independent clock enables are supported in the following clocking modes:
• Read/write clock mode—supported for both the read and write clocks.
• Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
Related Information
Guideline: Control Clocking to Reduce Power Consumption on page 2-7
Parity Bit in Memory Blocks
Table 2-11: Parity Bit Support for the Embedded Memory Blocks
This table describes the parity bit support for the memory blocks.
MLABM10K
• The parity bit is the ninth bit associated with each
byte.
• The ninth bit can store a parity bit or serve as an
additional bit.
• Parity function is not performed on the parity bit.
• The parity bit is the fifth bit associated with each
4 data bits in data widths of 5, 10, 20, and 40 (bits
4, 9, 14, 19, 24, 29, 34, and 39).
• In non-parity data widths, the parity bits are
skipped during read or write operations.
• Parity function is not performed on the parity bit.
Byte Enable in Embedded Memory Blocks
The embedded memory blocks support byte enable controls:
• The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten
bytes retain the values written previously.
•
The write enable (wren) signal, together with the byte enable (byteena) signal, control the write
operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren
signal controls the writing.
•
The byte enable registers do not have a clear port.
• If you are using parity bits, on the M10K blocks, the byte enable function controls 8 data bits and 2 parity
bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
•
The MSB and LSB of the byteena signal correspond to the MSB and LSB of the data bus, respectively.
• The byte enables are active high.
Byte Enable Controls in Memory Blocks
Table 2-12: byteena Controls in x20 Data Width
Data Bits Writtenbyteena[1:0]
[9:0][19:10]
11 (default)
—
[19:10]
10
Altera Corporation
Embedded Memory Blocks in Cyclone V Devices
Send Feedback
2-13
Independent Clock Enables in Clocking Modes
CV-52002
2013.05.06