Specifications

Memory Mode
Clocking Mode
FIFOROMTrue Dual-
Port
Simple Dual-
Port
Single-Port
—YesYesYesYesInput/output clock mode
—YesYes——Independent clock mode
The clock enable signals are not supported for write address, byte enable, and data input registers
on MLAB blocks.
Note:
Single Clock Mode
In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory
block.
Read/Write Clock Mode
In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls
the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address,
write-enable, and byte enable registers.
Input/Output Clock Mode
In input/output clock mode, a separate clock is available for each input and output port. An input clock
controls all registers related to the data input to the memory block including data, address, byte enables,
read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode
In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all
registers on the port A side; clock B controls all registers on the port B side.
You can create independent clock enable for different input and output registers to control the shut
down of a particular register for power saving purposes. From the parameter editor, click More
Options (beside the clock enable option) to set the available independent clock enable that you prefer.
Note:
Asynchronous Clears in Clocking Modes
In all clocking modes, asynchronous clears are available only for output latches and output registers. For
the independent clock mode, this is applicable on both ports.
Output Read Data in Simultaneous Read/Write
If you perform a simultaneous read/write to the same address location using the read/write clock mode, the
output read data is unknown. If you require the output read data to be a known value, use single-clock or
input/output clock mode and select the appropriate read-during-write behavior in the MegaWizard
™
Plug-
In Manager.
Embedded Memory Blocks in Cyclone V Devices
Altera Corporation
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Single Clock Mode
2-12
2013.05.06