Specifications

Description
MLAB
Support
M10K
SupportMemory Mode
You can use the memory blocks as ROM.
• Initialize the ROM contents of the memory blocks using a .mif
or .hex.
• The address lines of the ROM are registered on M10K blocks
but can be unregistered on MLABs.
• The outputs can be registered or unregistered.
• The output registers can be asynchronously cleared.
• The ROM read operation is identical to the read operation in
the single-port RAM configuration.
YesYesROM
You can use the memory blocks as FIFO buffers. Use the SCFIFO
and DCFIFO megafunctions to implement single- and dual-clock
asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the
MLABs are ideal for the FIFO mode. However, the MLABs do
not support mixed-width FIFO mode.
YesYesFIFO
Related Information
• Internal Memory (RAM and ROM) User Guide
Provides more information memory modes.
• RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide
Provides more information about implementing the shift register mode.
• SCFIFO and DCFIFO Megafunctions User Guide
Provides more information about implementing FIFO buffers.
Embedded Memory Clocking Modes
This section describes the clocking modes for the Cyclone V memory blocks.
To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations.
Caution:
Clocking Modes for Each Memory Mode
Table 2-10: Memory Blocks Clocking Modes Supported for Each Memory Mode
Memory Mode
Clocking Mode
FIFOROMTrue Dual-
Port
Simple Dual-
Port
Single-Port
YesYesYesYesYesSingle clock mode
Yes——Yes—Read/write clock mode
Altera Corporation
Embedded Memory Blocks in Cyclone V Devices
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2-11
Embedded Memory Clocking Modes
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2013.05.06